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PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter

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All callers of pci_bridge_wait_for_secondary_bus() supply a timeout of
PCIE_RESET_READY_POLL_MS, so drop the parameter.  Move the definition of
PCIE_RESET_READY_POLL_MS into pci.c, the only user.

[bhelgaas: extracted from
https://lore.kernel.org/r/20230404052714.51315-3-mika.westerberg@linux.intel.com]
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Mika Westerberg 2023-04-04 15:32:55 -05:00 committed by Bjorn Helgaas
parent e8b908146d
commit e74b2b58ff
4 changed files with 16 additions and 18 deletions
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4
drivers/pci/pci-driver.c
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@ -572,8 +572,8 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev)
static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev) static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)
{ {
pci_bridge_wait_for_secondary_bus(pci_dev, "resume", pci_bridge_wait_for_secondary_bus(pci_dev, "resume");
PCIE_RESET_READY_POLL_MS);
/* /*
* When powering on a bridge from D3cold, the whole hierarchy may be * When powering on a bridge from D3cold, the whole hierarchy may be
* powered on into D0uninitialized state, resume them to give them a * powered on into D0uninitialized state, resume them to give them a

18
drivers/pci/pci.c
View File

@ -64,6 +64,14 @@ struct pci_pme_device {
#define PME_TIMEOUT 1000 /* How long between PME checks */ #define PME_TIMEOUT 1000 /* How long between PME checks */
/*
* Devices may extend the 1 sec period through Request Retry Status
* completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
* limit, but 60 sec ought to be enough for any device to become
* responsive.
*/
#define PCIE_RESET_READY_POLL_MS 60000 /* msec */
static void pci_dev_d3_sleep(struct pci_dev *dev) static void pci_dev_d3_sleep(struct pci_dev *dev)
{ {
unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
@ -4939,7 +4947,6 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
* pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
* @dev: PCI bridge * @dev: PCI bridge
* @reset_type: reset type in human-readable form * @reset_type: reset type in human-readable form
* @timeout: maximum time to wait for devices on secondary bus (milliseconds)
* *
* Handle necessary delays before access to the devices on the secondary * Handle necessary delays before access to the devices on the secondary
* side of the bridge are permitted after D3cold to D0 transition * side of the bridge are permitted after D3cold to D0 transition
@ -4952,8 +4959,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
* Return 0 on success or -ENOTTY if the first device on the secondary bus * Return 0 on success or -ENOTTY if the first device on the secondary bus
* failed to become accessible. * failed to become accessible.
*/ */
int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type, int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
int timeout)
{ {
struct pci_dev *child; struct pci_dev *child;
int delay; int delay;
@ -5031,7 +5037,8 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
} }
} }
return pci_dev_wait(child, reset_type, timeout - delay); return pci_dev_wait(child, reset_type,
PCIE_RESET_READY_POLL_MS - delay);
} }
void pci_reset_secondary_bus(struct pci_dev *dev) void pci_reset_secondary_bus(struct pci_dev *dev)
@ -5068,8 +5075,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
{ {
pcibios_reset_secondary_bus(dev); pcibios_reset_secondary_bus(dev);
return pci_bridge_wait_for_secondary_bus(dev, "bus reset", return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
PCIE_RESET_READY_POLL_MS);
} }
EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);

9
drivers/pci/pci.h
View File

@ -70,12 +70,6 @@ struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
* Reset (PCIe r6.0 sec 5.8). * Reset (PCIe r6.0 sec 5.8).
*/ */
#define PCI_RESET_WAIT 1000 /* msec */ #define PCI_RESET_WAIT 1000 /* msec */
/*
* Devices may extend the 1 sec period through Request Retry Status completions
* (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
* ought to be enough for any device to become responsive.
*/
#define PCIE_RESET_READY_POLL_MS 60000 /* msec */
void pci_update_current_state(struct pci_dev *dev, pci_power_t state); void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
void pci_refresh_power_state(struct pci_dev *dev); void pci_refresh_power_state(struct pci_dev *dev);
@ -100,8 +94,7 @@ void pci_msix_init(struct pci_dev *dev);
bool pci_bridge_d3_possible(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev);
void pci_bridge_d3_update(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev);
void pci_bridge_reconfigure_ltr(struct pci_dev *dev); void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type, int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
int timeout);
static inline void pci_wakeup_event(struct pci_dev *dev) static inline void pci_wakeup_event(struct pci_dev *dev)
{ {

3
drivers/pci/pcie/dpc.c
View File

@ -170,8 +170,7 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
PCI_EXP_DPC_STATUS_TRIGGER); PCI_EXP_DPC_STATUS_TRIGGER);
if (pci_bridge_wait_for_secondary_bus(pdev, "DPC", if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {
PCIE_RESET_READY_POLL_MS)) {
clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
ret = PCI_ERS_RESULT_DISCONNECT; ret = PCI_ERS_RESULT_DISCONNECT;
} else { } else {