arm64: Switch to PMR masking when starting CPUs
Once the boot CPU has been prepared or a new secondary CPU has been brought up, use ICC_PMR_EL1 to mask interrupts on that CPU and clear PSR.I bit. Since ICC_PMR_EL1 is initialized at CPU bringup, avoid overwriting it in the GICv3 driver. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -35,6 +35,7 @@
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#include <linux/smp.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/percpu.h>
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#include <linux/clockchips.h>
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#include <linux/completion.h>
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@ -180,6 +181,24 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
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return ret;
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}
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static void init_gic_priority_masking(void)
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{
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u32 cpuflags;
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if (WARN_ON(!gic_enable_sre()))
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return;
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cpuflags = read_sysreg(daif);
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WARN_ON(!(cpuflags & PSR_I_BIT));
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gic_write_pmr(GIC_PRIO_IRQOFF);
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/* We can only unmask PSR.I if we can take aborts */
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if (!(cpuflags & PSR_A_BIT))
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write_sysreg(cpuflags & ~PSR_I_BIT, daif);
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}
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/*
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* This is the secondary CPU boot entry. We're using this CPUs
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* idle thread stack, but a set of temporary page tables.
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@ -206,6 +225,9 @@ asmlinkage notrace void secondary_start_kernel(void)
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*/
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cpu_uninstall_idmap();
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if (system_uses_irq_prio_masking())
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init_gic_priority_masking();
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preempt_disable();
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trace_hardirqs_off();
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@ -426,6 +448,10 @@ void __init smp_prepare_boot_cpu(void)
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* and/or scheduling is enabled.
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*/
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apply_boot_alternatives();
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/* Conditionally switch to GIC PMR for interrupt masking */
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if (system_uses_irq_prio_masking())
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init_gic_priority_masking();
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}
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static u64 __init of_get_cpu_mpidr(struct device_node *dn)
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@ -415,6 +415,9 @@ static u32 gic_get_pribits(void)
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static bool gic_has_group0(void)
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{
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u32 val;
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u32 old_pmr;
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old_pmr = gic_read_pmr();
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/*
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* Let's find out if Group0 is under control of EL3 or not by
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@ -430,6 +433,8 @@ static bool gic_has_group0(void)
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gic_write_pmr(BIT(8 - gic_get_pribits()));
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val = gic_read_pmr();
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gic_write_pmr(old_pmr);
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return val != 0;
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}
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@ -591,6 +596,7 @@ static void gic_cpu_sys_reg_init(void)
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group0 = gic_has_group0();
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/* Set priority mask register */
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if (!gic_prio_masking_enabled())
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write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
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/*
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