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ARM: dts: STiH410-family: fix wrong parent clock frequency

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[ Upstream commit b9ec866d223f38eb0bf2a7c836e10031ee17f7af ]

The clock parent was lower than child clock which is not correct.
In some use case, it leads to division by zero.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Patrice Chotard 2017-01-06 14:30:21 +01:00 committed by Greg Kroah-Hartman
parent d369bba844
commit e793ad50d1
1 changed files with 1 additions and 1 deletions
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arch/arm/boot/dts/stih410.dtsi
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@ -131,7 +131,7 @@
<&clk_s_d2_quadfs 0>;
assigned-clock-rates = <297000000>,
<108000000>,
<297000000>,
<0>,
<400000000>,
<400000000>;