riscv: dts: starfive: jh7110: add the node and pins configuration for tdm
Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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@ -315,6 +315,46 @@
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slew-rate = <0>;
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};
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};
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tdm_pins: tdm-0 {
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tx-pins {
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pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-pull-up;
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drive-strength = <2>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pinmux = <GPIOMUX(61, GPOUT_HIGH,
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GPOEN_DISABLE,
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GPI_SYS_TDM_RXD)>;
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input-enable;
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};
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sync-pins {
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pinmux = <GPIOMUX(63, GPOUT_HIGH,
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GPOEN_DISABLE,
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GPI_SYS_TDM_SYNC)>;
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input-enable;
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};
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pcmclk-pins {
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pinmux = <GPIOMUX(38, GPOUT_HIGH,
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GPOEN_DISABLE,
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GPI_SYS_TDM_CLK)>;
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input-enable;
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};
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};
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};
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&tdm {
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pinctrl-names = "default";
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pinctrl-0 = <&tdm_pins>;
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status = "okay";
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};
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&uart0 {
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@ -325,7 +365,6 @@
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&usb0 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&U74_1 {
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@ -491,6 +491,27 @@
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status = "disabled";
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};
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tdm: tdm@10090000 {
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compatible = "starfive,jh7110-tdm";
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reg = <0x0 0x10090000 0x0 0x1000>;
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clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
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<&syscrg JH7110_SYSCLK_TDM_APB>,
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<&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
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<&syscrg JH7110_SYSCLK_TDM_TDM>,
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<&syscrg JH7110_SYSCLK_MCLK_INNER>,
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<&tdm_ext>;
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clock-names = "tdm_ahb", "tdm_apb",
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"tdm_internal", "tdm",
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"mclk_inner", "tdm_ext";
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resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
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<&syscrg JH7110_SYSRST_TDM_APB>,
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<&syscrg JH7110_SYSRST_TDM_CORE>;
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dmas = <&dma 20>, <&dma 21>;
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dma-names = "rx","tx";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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usb0: usb@10100000 {
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compatible = "starfive,jh7110-usb";
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ranges = <0x0 0x0 0x10100000 0x100000>;
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