dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
The bindings describe the ZynqMP DP subsystem. They don't support the interface with the programmable logic (FPGA) or audio yet. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sam Ravnborg <sam@ravnborg.org>
This commit is contained in:
Hyun Kwon
Laurent Pinchart
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP DisplayPort Subsystem
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description: |
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The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
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implements the display and audio pipelines based on the DisplayPort v1.2
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standard. The subsystem includes multiple functional blocks as below:
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+------------------------------------------------------------+
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+--------+ | +----------------+ +-----------+ |
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| DPDMA | --->| | --> | Video | Video +-------------+ |
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| 4x vid | | | | | Rendering | -+--> | | | +------+
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| 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
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+--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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| | and STC | +-----------+ | | Controller | | +------+
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Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
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| | | | Mixer | --+-> | | | +------+
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Live Audio --->| | --> | | || +-------------+ |
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| +----------------+ +-----------+ || |
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+---------------------------------------||-------------------+
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vv
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Blended Video and
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Mixed Audio to PL
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The Buffer Manager interacts with external interface such as DMA engines or
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live audio/video streams from the programmable logic. The Video Rendering
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Pipeline blends the video and graphics layers and performs colorspace
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conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
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Source Controller handles the DisplayPort protocol and connects to external
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PHYs.
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The subsystem supports 2 video and 2 audio streams, and various pixel formats
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and depths up to 4K@30 resolution.
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Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
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(https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
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for more details.
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maintainers:
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- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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properties:
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compatible:
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const: xlnx,zynqmp-dpsub-1.7
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: dp
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- const: blend
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- const: av_buf
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- const: aud
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interrupts:
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maxItems: 1
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clocks:
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description:
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The APB clock and at least one video clock are mandatory, the audio clock
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is optional.
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minItems: 2
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maxItems: 4
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items:
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- description: dp_apb_clk is the APB clock
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- description: dp_aud_clk is the Audio clock
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- description:
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dp_vtc_pixel_clk_in is the non-live video clock (from Processing
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System)
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- description:
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dp_live_video_in_clk is the live video clock (from Programmable
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Logic)
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clock-names:
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oneOf:
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- minItems: 2
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maxItems: 3
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items:
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- const: dp_apb_clk
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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- minItems: 3
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maxItems: 4
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items:
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- const: dp_apb_clk
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- const: dp_aud_clk
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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dmas:
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maxItems: 4
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items:
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- description: Video layer, plane 0 (RGB or luma)
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- description: Video layer, plane 1 (U/V or U)
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- description: Video layer, plane 2 (V)
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- description: Graphics layer
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dma-names:
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items:
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- const: vid0
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- const: vid1
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- const: vid2
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- const: gfx0
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phys:
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description: PHYs for the DP data lanes
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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- const: dp-phy0
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- const: dp-phy1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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- dmas
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- dma-names
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- phys
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- phy-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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display@fd4a0000 {
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compatible = "xlnx,zynqmp-dpsub-1.7";
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reg = <0x0 0xfd4a0000 0x0 0x1000>,
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<0x0 0xfd4aa000 0x0 0x1000>,
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<0x0 0xfd4ab000 0x0 0x1000>,
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<0x0 0xfd4ac000 0x0 0x1000>;
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reg-names = "dp", "blend", "av_buf", "aud";
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interrupts = <0 119 4>;
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interrupt-parent = <&gic>;
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clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
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clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
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power-domains = <&pd_dp>;
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resets = <&reset ZYNQMP_RESET_DP>;
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dma-names = "vid0", "vid1", "vid2", "gfx0";
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dmas = <&xlnx_dpdma 0>,
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<&xlnx_dpdma 1>,
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<&xlnx_dpdma 2>,
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<&xlnx_dpdma 3>;
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phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,
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<&psgtr 0 PHY_TYPE_DP 1 3 27000000>;
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phy-names = "dp-phy0", "dp-phy1";
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};
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...
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