iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel-pinctrl for v6.2-2

Browse Source 
* Enable PWM feature on Intel pin control IPs
 
 The following is an automated git shortlog grouped by driver:
 
 intel:
  -  Enumerate PWM device when community has a capability
 
 pwm:
  -  lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
  -  lpss: Allow other drivers to enable PWM LPSS
  -  lpss: Include headers we are the direct user of
  -  lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
  -  Add a stub for devm_pwmchip_add()
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmN9Fn8ACgkQb7wzTHR8
 rCh+7RAAqQjDQi6wGEXnjWTKA0OGCoi5uqrpuCa1g1Mr+57ym9BmMHCuK3U5UWkK
 cXdXq15FulfIM75v8XeKGzWjG+N9AKjrgAqnV9RU+CwQeB7ROM5vgm3+JrJOEs/n
 96rtvC1wD46MvKQ9gqv57GiyI3gKQuUKM5AnofPE/tcQAINx6W+82/xO3tWzH+LY
 ZTSywCEzXuMLsOBlg4GfUHS0YuN8g7go2VZ7n+D38+jR090/xwdCfLXT0VMc9i+D
 lFI/1CwLGqHAVw+loUTKEZ1cQ9bOOEa618/kkQ501n24LZ+3PzdJpvA7wvR/0sjM
 e6tooa6Lb7V00oxxADVY7+a4VEmBgy1n9ExJFgrC03iNal7ALY2oZvloWpyl0iYf
 cAqqNiKLsuU+J1i/mMqXxlMcrZyb/5BUBzAPgrDIhu2sVtuVCXIoTPNfjkK6TaGx
 4gRA3NzSoNkF554BCPdVSm2BsGos30yVRSN3hn4S9w+hzo3l4DmZzXBvDsxT3BhB
 wSbXOQ1Fx65kwQRZWVyxj4+i7XTzWzc6ZOxuRN7JKclYyfN5jptqDfngczToNU67
 rTZuSLP99lVrKIjTrhd3Fpq+c1VhfMndNAcT2kKJ89uMIvpUK8AcxYFR28JAqxjj
 sdoUOo46o+4R9o+7vR3G1QJsWID5ZYyRBWIOxqRdXIKf9joP91Y=
 =ewrB
 -----END PGP SIGNATURE-----

Merge tag 'intel-pinctrl-v6.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v6.2-2

* Enable PWM feature on Intel pin control IPs

The following is an automated git shortlog grouped by driver:

intel:
 -  Enumerate PWM device when community has a capability

pwm:
 -  lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
 -  lpss: Allow other drivers to enable PWM LPSS
 -  lpss: Include headers we are the direct user of
 -  lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
 -  Add a stub for devm_pwmchip_add()
This commit is contained in:
Linus Walleij 2022-11-28 21:23:20 +01:00
commit e7d0040b43
7 changed files with 77 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -24,6 +24,8 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_data/x86/pwm-lpss.h>
#include "../core.h"
#include "pinctrl-intel.h"
@ -49,6 +51,8 @@
#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
#define PADOWN_GPP(p) ((p) / 8)
#define PWMC 0x204
/* Offset from pad_regs */
#define PADCFG0 0x000
#define PADCFG0_RXEVCFG_SHIFT 25
@ -1502,6 +1506,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return 0;
}
static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
struct intel_community *community)
{
static const struct pwm_lpss_boardinfo info = {
.clk_rate = 19200000,
.npwm = 1,
.base_unit_bits = 22,
.bypass = true,
};
struct pwm_lpss_chip *pwm;
if (!(community->features & PINCTRL_FEATURE_PWM))
return 0;
if (!IS_REACHABLE(CONFIG_PWM_LPSS))
return 0;
pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
return PTR_ERR_OR_ZERO(pwm);
}
static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
@ -1588,6 +1613,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
if (ret)
return ret;
ret = intel_pinctrl_probe_pwm(pctrl, community);
if (ret)
return ret;
}
irq = platform_get_irq(pdev, 0);

2
drivers/pwm/pwm-lpss-pci.c
View File

@ -30,7 +30,7 @@ static int pwm_lpss_probe_pci(struct pci_dev *pdev,
return err;
info = (struct pwm_lpss_boardinfo *)id->driver_data;
lpwm = pwm_lpss_probe(&pdev->dev, pcim_iomap_table(pdev)[0], info);
lpwm = devm_pwm_lpss_probe(&pdev->dev, pcim_iomap_table(pdev)[0], info);
if (IS_ERR(lpwm))
return PTR_ERR(lpwm);

2
drivers/pwm/pwm-lpss-platform.c
View File

@ -31,7 +31,7 @@ static int pwm_lpss_probe_platform(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
lpwm = pwm_lpss_probe(&pdev->dev, base, info);
lpwm = devm_pwm_lpss_probe(&pdev->dev, base, info);
if (IS_ERR(lpwm))
return PTR_ERR(lpwm);

8
drivers/pwm/pwm-lpss.c
View File

@ -244,15 +244,15 @@ static const struct pwm_ops pwm_lpss_ops = {
.owner = THIS_MODULE,
};
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info)
struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info)
{
struct pwm_lpss_chip *lpwm;
unsigned long c;
int i, ret;
u32 ctrl;
if (WARN_ON(info->npwm > MAX_PWMS))
if (WARN_ON(info->npwm > LPSS_MAX_PWMS))
return ERR_PTR(-ENODEV);
lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
@ -284,7 +284,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
return lpwm;
}
EXPORT_SYMBOL_GPL(pwm_lpss_probe);
EXPORT_SYMBOL_GPL(devm_pwm_lpss_probe);
MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");

26
drivers/pwm/pwm-lpss.h
View File

@ -10,10 +10,12 @@
#ifndef __PWM_LPSS_H
#define __PWM_LPSS_H
#include <linux/device.h>
#include <linux/pwm.h>
#include <linux/types.h>
#define MAX_PWMS 4
#include <linux/platform_data/x86/pwm-lpss.h>
#define LPSS_MAX_PWMS 4
struct pwm_lpss_chip {
struct pwm_chip chip;
@ -21,29 +23,9 @@ struct pwm_lpss_chip {
const struct pwm_lpss_boardinfo *info;
};
struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
unsigned long base_unit_bits;
/*
* Some versions of the IP may stuck in the state machine if enable
* bit is not set, and hence update bit will show busy status till
* the reset. For the rest it may be otherwise.
*/
bool bypass;
/*
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
* messes with the PWM0 controllers state,
*/
bool other_devices_aml_touches_pwm_regs;
};
extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info;
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info);
#endif /* __PWM_LPSS_H */

33
include/linux/platform_data/x86/pwm-lpss.h Normal file
View File

@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Intel Low Power Subsystem PWM controller driver */
#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H
#define __PLATFORM_DATA_X86_PWM_LPSS_H
#include <linux/types.h>
struct device;
struct pwm_lpss_chip;
struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
unsigned long base_unit_bits;
/*
* Some versions of the IP may stuck in the state machine if enable
* bit is not set, and hence update bit will show busy status till
* the reset. For the rest it may be otherwise.
*/
bool bypass;
/*
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
* messes with the PWM0 controllers state,
*/
bool other_devices_aml_touches_pwm_regs;
};
struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info);
#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */

5
include/linux/pwm.h
View File

@ -478,6 +478,11 @@ static inline int pwmchip_remove(struct pwm_chip *chip)
return -EINVAL;
}
static inline int devm_pwmchip_add(struct device *dev, struct pwm_chip *chip)
{
return -EINVAL;
}
static inline struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
unsigned int index,
const char *label)