ARM: 7207/1: Use generic ARM instruction set condition code checks for nwfpe.
This patch changes the nwfpe implementation to use the new generic ARM instruction set condition code checks, rather than a local implementation. It also removes the existing condition code checking, which has been used for the generic support (in kernel/opcodes.{ch}). This code has not been tested beyond building, linking and booting. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -20,6 +20,8 @@
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#include <asm/opcodes.h>
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/* This is the kernel's entry point into the floating point emulator.
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/* This is the kernel's entry point into the floating point emulator.
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It is called from the kernel with code similar to this:
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It is called from the kernel with code similar to this:
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@ -81,11 +83,11 @@ nwfpe_enter:
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mov r6, r0 @ save the opcode
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mov r6, r0 @ save the opcode
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emulate:
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emulate:
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ldr r1, [sp, #S_PSR] @ fetch the PSR
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ldr r1, [sp, #S_PSR] @ fetch the PSR
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bl checkCondition @ check the condition
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bl arm_check_condition @ check the condition
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cmp r0, #0 @ r0 = 0 ==> condition failed
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cmp r0, #ARM_OPCODE_CONDTEST_PASS @ condition passed?
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@ if condition code failed to match, next insn
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@ if condition code failed to match, next insn
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beq next @ get the next instruction;
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bne next @ get the next instruction;
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mov r0, r6 @ prepare for EmulateAll()
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mov r0, r6 @ prepare for EmulateAll()
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bl EmulateAll @ emulate the instruction
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bl EmulateAll @ emulate the instruction
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@ -61,29 +61,3 @@ const float32 float32Constant[] = {
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0x41200000 /* single 10.0 */
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0x41200000 /* single 10.0 */
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};
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};
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/* condition code lookup table
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index into the table is test code: EQ, NE, ... LT, GT, AL, NV
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bit position in short is condition code: NZCV */
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static const unsigned short aCC[16] = {
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0xF0F0, // EQ == Z set
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0x0F0F, // NE
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0xCCCC, // CS == C set
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0x3333, // CC
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0xFF00, // MI == N set
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0x00FF, // PL
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0xAAAA, // VS == V set
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0x5555, // VC
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0x0C0C, // HI == C set && Z clear
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0xF3F3, // LS == C clear || Z set
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0xAA55, // GE == (N==V)
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0x55AA, // LT == (N!=V)
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0x0A05, // GT == (!Z && (N==V))
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0xF5FA, // LE == (Z || (N!=V))
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0xFFFF, // AL always
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0 // NV
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};
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unsigned int checkCondition(const unsigned int opcode, const unsigned int ccodes)
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{
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return (aCC[opcode >> 28] >> (ccodes >> 28)) & 1;
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}
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@ -475,9 +475,6 @@ static inline unsigned int getDestinationSize(const unsigned int opcode)
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return (nRc);
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return (nRc);
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}
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}
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extern unsigned int checkCondition(const unsigned int opcode,
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const unsigned int ccodes);
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extern const float64 float64Constant[];
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extern const float64 float64Constant[];
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extern const float32 float32Constant[];
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extern const float32 float32Constant[];
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