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clk: meson: axg: add MIPI DSI Host clock

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This adds the MIPI DSI Host clock, used to measure the signal timings
(ENC VSYNC or DW-MIPI-DSI eDPI timings).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200915124553.8056-5-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong 2020-09-15 14:45:53 +02:00 committed by Jerome Brunet
parent 14ebb3154b
commit e80d8510ff
2 changed files with 69 additions and 1 deletions
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66
drivers/clk/meson/axg.c
View File

@ -1703,6 +1703,66 @@ static struct clk_regmap axg_cts_encl = {
},
};
/* MIPI DSI Host Clock */
static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
{ .fw_name = "xtal", },
{ .hw = &axg_fclk_div4.hw },
{ .hw = &axg_fclk_div3.hw },
{ .hw = &axg_fclk_div5.hw },
{ .hw = &axg_fclk_div2.hw },
{ .hw = &axg_fclk_div7.hw },
};
static struct clk_regmap axg_vdin_meas_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VDIN_MEAS_CLK_CNTL,
.mask = 0x7,
.shift = 21,
.flags = CLK_MUX_ROUND_CLOSEST,
.table = mux_table_axg_vdin_meas,
},
.hw.init = &(struct clk_init_data){
.name = "vdin_meas_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = axg_vdin_meas_parent_data,
.num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_vdin_meas_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_VDIN_MEAS_CLK_CNTL,
.shift = 12,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "vdin_meas_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_vdin_meas_sel.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_vdin_meas = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VDIN_MEAS_CLK_CNTL,
.bit_idx = 20,
},
.hw.init = &(struct clk_init_data) {
.name = "vdin_meas",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_vdin_meas_div.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9, 10, 11, 13, 14, };
static const struct clk_parent_data gen_clk_parent_data[] = {
@ -1966,6 +2026,9 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
[CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
[CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@ -2094,6 +2157,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_vclk2_div12_en,
&axg_cts_encl_sel,
&axg_cts_encl,
&axg_vdin_meas_sel,
&axg_vdin_meas_div,
&axg_vdin_meas,
};
static const struct meson_eeclkc_data axg_clkc_data = {

4
drivers/clk/meson/axg.h
View File

@ -158,8 +158,10 @@
#define CLKID_VCLK2_DIV6_EN 120
#define CLKID_VCLK2_DIV12_EN 121
#define CLKID_CTS_ENCL_SEL 132
#define CLKID_VDIN_MEAS_SEL 134
#define CLKID_VDIN_MEAS_DIV 135
#define NR_CLKS 134
#define NR_CLKS 137
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>