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drm/xe: Restrict huge PTEs to 1GiB

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Add a define for the highest level for which we can encode a huge PTE,
and use it for page-table building. Also update an assert that checks that
we don't try to encode for larger sizes.

Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Brian Welty <brian.welty@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231209151843.7903-2-thomas.hellstrom@linux.intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Thomas Hellström 2023-12-09 16:18:41 +01:00 committed by Rodrigo Vivi
parent 1c8e901903
commit e84d716dd4
3 changed files with 7 additions and 1 deletions
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3
drivers/gpu/drm/xe/xe_pt.c
View File

@ -430,6 +430,9 @@ static bool xe_pt_hugepte_possible(u64 addr, u64 next, unsigned int level,
{ {
u64 size, dma; u64 size, dma;
if (level > MAX_HUGEPTE_LEVEL)
return false;
/* Does the virtual range requested cover a huge pte? */ /* Does the virtual range requested cover a huge pte? */
if (!xe_pt_covers(addr, next, level, &xe_walk->base)) if (!xe_pt_covers(addr, next, level, &xe_walk->base))
return false; return false;

3
drivers/gpu/drm/xe/xe_pt.h
View File

@ -18,6 +18,9 @@ struct xe_tile;
struct xe_vm; struct xe_vm;
struct xe_vma; struct xe_vma;
/* Largest huge pte is currently 1GiB. May become device dependent. */
#define MAX_HUGEPTE_LEVEL 2
#define xe_pt_write(xe, map, idx, data) \ #define xe_pt_write(xe, map, idx, data) \
xe_map_wr(xe, map, (idx) * sizeof(u64), u64, data) xe_map_wr(xe, map, (idx) * sizeof(u64), u64, data)

2
drivers/gpu/drm/xe/xe_vm.c
View File

@ -1258,7 +1258,7 @@ static u64 pte_encode_pat_index(struct xe_device *xe, u16 pat_index,
static u64 pte_encode_ps(u32 pt_level) static u64 pte_encode_ps(u32 pt_level)
{ {
XE_WARN_ON(pt_level > 2); XE_WARN_ON(pt_level > MAX_HUGEPTE_LEVEL);
if (pt_level == 1) if (pt_level == 1)
return XE_PDE_PS_2M; return XE_PDE_PS_2M;