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ARM: 8838/1: drivers: amba: Updates to component identification for driver matching.

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The CoreSight specification (ARM IHI 0029E), updates the ID register
requirements for components on an AMBA bus, to cover both traditional
ARM Primecell type devices, and newer CoreSight and other components.

The Peripheral ID (PID) / Component ID (CID) pair is extended in certain
cases to uniquely identify components. CoreSight components related to
a single function can share Peripheral ID values, and must be further
identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI,
PMU and Debug hardware of the A35 all share the same PID.

Bits 15:12 of the CID are defined to be the device class.
Class 0xF remains for PrimeCell and legacy components.
Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
at present.
Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.

The specification futher defines which classes of device use the standard
CID/PID pair, and when additional ID registers are required.

This patch introduces the amba_cs_uci_id structure which will be used in
all coresight drivers for indentification via the private data pointer in
the amba_id structure.

Existing drivers that currently use the amba_id->data pointer for private
data are updated to use the amba_cs_uci_id->data pointer. Macros and
inline functions are added to simplify this code.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Mike Leach 2019-02-13 14:41:49 +01:00 committed by Russell King
parent de9c0d49d8
commit e85fa28ebc
5 changed files with 90 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
drivers/hwtracing/coresight/coresight-etm3x.c
View File

@ -871,7 +871,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
}
pm_runtime_put(&adev->dev);
dev_info(dev, "%s initialized\n", (char *)id->data);
dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id));
if (boot_enable) {
coresight_enable(drvdata->csdev);
drvdata->boot_enable = true;
@ -915,36 +915,18 @@ static const struct dev_pm_ops etm_dev_pm_ops = {
};
static const struct amba_id etm_ids[] = {
{ /* ETM 3.3 */
.id = 0x000bb921,
.mask = 0x000fffff,
.data = "ETM 3.3",
},
{ /* ETM 3.5 - Cortex-A5 */
.id = 0x000bb955,
.mask = 0x000fffff,
.data = "ETM 3.5",
},
{ /* ETM 3.5 */
.id = 0x000bb956,
.mask = 0x000fffff,
.data = "ETM 3.5",
},
{ /* PTM 1.0 */
.id = 0x000bb950,
.mask = 0x000fffff,
.data = "PTM 1.0",
},
{ /* PTM 1.1 */
.id = 0x000bb95f,
.mask = 0x000fffff,
.data = "PTM 1.1",
},
{ /* PTM 1.1 Qualcomm */
.id = 0x000b006f,
.mask = 0x000fffff,
.data = "PTM 1.1",
},
/* ETM 3.3 */
CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"),
/* ETM 3.5 - Cortex-A5 */
CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"),
/* ETM 3.5 */
CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"),
/* PTM 1.0 */
CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"),
/* PTM 1.1 */
CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"),
/* PTM 1.1 Qualcomm */
CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"),
{ 0, 0},
};

32
drivers/hwtracing/coresight/coresight-priv.h
View File

@ -6,6 +6,7 @@
#ifndef _CORESIGHT_PRIV_H
#define _CORESIGHT_PRIV_H
#include <linux/amba/bus.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/coresight.h>
@ -159,4 +160,35 @@ static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
#endif
/*
* Macros and inline functions to handle CoreSight UCI data and driver
* private data in AMBA ID table entries, and extract data values.
*/
/* coresight AMBA ID, no UCI, no driver data: id table entry */
#define CS_AMBA_ID(pid) \
{ \
.id = pid, \
.mask = 0x000fffff, \
}
/* coresight AMBA ID, UCI with driver data only: id table entry. */
#define CS_AMBA_ID_DATA(pid, dval) \
{ \
.id = pid, \
.mask = 0x000fffff, \
.data = (void *)&(struct amba_cs_uci_id) \
{ \
.data = (void *)dval, \
} \
}
/* extract the data value from a UCI structure given amba_id pointer. */
static inline void *coresight_get_uci_data(const struct amba_id *id)
{
if (id->data)
return ((struct amba_cs_uci_id *)(id->data))->data;
return 0;
}
#endif

14
drivers/hwtracing/coresight/coresight-stm.c
View File

@ -874,7 +874,7 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id)
pm_runtime_put(&adev->dev);
dev_info(dev, "%s initialized\n", (char *)id->data);
dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id));
return 0;
stm_unregister:
@ -909,16 +909,8 @@ static const struct dev_pm_ops stm_dev_pm_ops = {
};
static const struct amba_id stm_ids[] = {
{
.id = 0x000bb962,
.mask = 0x000fffff,
.data = "STM32",
},
{
.id = 0x000bb963,
.mask = 0x000fffff,
.data = "STM500",
},
CS_AMBA_ID_DATA(0x000bb962, "STM32"),
CS_AMBA_ID_DATA(0x000bb963, "STM500"),
{ 0, 0},
};

30
drivers/hwtracing/coresight/coresight-tmc.c
View File

@ -443,7 +443,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
desc.type = CORESIGHT_DEV_TYPE_SINK;
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
desc.ops = &tmc_etr_cs_ops;
ret = tmc_etr_setup_caps(drvdata, devid, id->data);
ret = tmc_etr_setup_caps(drvdata, devid,
coresight_get_uci_data(id));
if (ret)
goto out;
break;
@ -475,26 +476,13 @@ out:
}
static const struct amba_id tmc_ids[] = {
{
.id = 0x000bb961,
.mask = 0x000fffff,
},
{
/* Coresight SoC 600 TMC-ETR/ETS */
.id = 0x000bb9e8,
.mask = 0x000fffff,
.data = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
},
{
/* Coresight SoC 600 TMC-ETB */
.id = 0x000bb9e9,
.mask = 0x000fffff,
},
{
/* Coresight SoC 600 TMC-ETF */
.id = 0x000bb9ea,
.mask = 0x000fffff,
},
CS_AMBA_ID(0x000bb961),
/* Coresight SoC 600 TMC-ETR/ETS */
CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
/* Coresight SoC 600 TMC-ETB */
CS_AMBA_ID(0x000bb9e9),
/* Coresight SoC 600 TMC-ETF */
CS_AMBA_ID(0x000bb9ea),
{ 0, 0},
};

33
include/linux/amba/bus.h
View File

@ -25,6 +25,39 @@
#define AMBA_CID 0xb105f00d
#define CORESIGHT_CID 0xb105900d
/*
* CoreSight Architecture specification updates the ID specification
* for components on the AMBA bus. (ARM IHI 0029E)
*
* Bits 15:12 of the CID are the device class.
*
* Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above)
* Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
* Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
* at present.
* Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
*
* Remaining CID bits stay as 0xb105-00d
*/
/**
* Class 0x9 components use additional values to form a Unique Component
* Identifier (UCI), where peripheral ID values are identical for different
* components. Passed to the amba bus code from the component driver via
* the amba_id->data pointer.
* @devarch : coresight devarch register value
* @devarch_mask: mask bits used for matching. 0 indicates UCI not used.
* @devtype : coresight device type value
* @data : additional driver data. As we have usurped the original
* pointer some devices may still need additional data
*/
struct amba_cs_uci_id {
unsigned int devarch;
unsigned int devarch_mask;
unsigned int devtype;
void *data;
};
struct clk;
struct amba_device {