drivers: usb: dwc3: Add AM62 USB wrapper driver
In AM62 SoC, the Designware Core USB3 IP is progammed to operate in USB2.0 only mode. Add driver for AM62 USB DWC3 Wrapper. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20220414103211.16202-3-a-govindraju@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Aswath Govindraju
Greg Kroah-Hartman
parent
ee11ae36b2
commit
e8784c0aec
@ -159,4 +159,13 @@ config USB_DWC3_XILINX
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This driver handles both ZynqMP and Versal SoC operations.
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Say 'Y' or 'M' if you have one such device.
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config USB_DWC3_AM62
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tristate "Texas Instruments AM62 Platforms"
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depends on ARCH_K3 || COMPILE_TEST
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default USB_DWC3
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help
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Support TI's AM62 platforms with DesignWare Core USB3 IP.
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The Designware Core USB3 IP is progammed to operate in
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in USB 2.0 mode only.
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Say 'Y' or 'M' here if you have one such device
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endif
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@ -42,6 +42,7 @@ endif
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# and allyesconfig builds.
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##
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obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o
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obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
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obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
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obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
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332
drivers/usb/dwc3/dwc3-am62.c
Normal file
332
drivers/usb/dwc3/dwc3-am62.c
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@ -0,0 +1,332 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
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*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/pinctrl/consumer.h>
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/* USB WRAPPER register offsets */
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#define USBSS_PID 0x0
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#define USBSS_OVERCURRENT_CTRL 0x4
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#define USBSS_PHY_CONFIG 0x8
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#define USBSS_PHY_TEST 0xc
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#define USBSS_CORE_STAT 0x14
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#define USBSS_HOST_VBUS_CTRL 0x18
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#define USBSS_MODE_CONTROL 0x1c
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#define USBSS_WAKEUP_CONFIG 0x30
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#define USBSS_WAKEUP_STAT 0x34
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#define USBSS_OVERRIDE_CONFIG 0x38
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#define USBSS_IRQ_MISC_STATUS_RAW 0x430
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#define USBSS_IRQ_MISC_STATUS 0x434
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#define USBSS_IRQ_MISC_ENABLE_SET 0x438
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#define USBSS_IRQ_MISC_ENABLE_CLR 0x43c
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#define USBSS_IRQ_MISC_EOI 0x440
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#define USBSS_INTR_TEST 0x490
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#define USBSS_VBUS_FILTER 0x614
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#define USBSS_VBUS_STAT 0x618
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#define USBSS_DEBUG_CFG 0x708
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#define USBSS_DEBUG_DATA 0x70c
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#define USBSS_HOST_HUB_CTRL 0x714
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/* PHY CONFIG register bits */
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#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1)
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#define USBSS_PHY_VBUS_SEL_SHIFT 1
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#define USBSS_PHY_LANE_REVERSE BIT(0)
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/* MODE CONTROL register bits */
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#define USBSS_MODE_VALID BIT(0)
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/* WAKEUP CONFIG register bits */
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#define USBSS_WAKEUP_CFG_OVERCURRENT_EN BIT(3)
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#define USBSS_WAKEUP_CFG_LINESTATE_EN BIT(2)
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#define USBSS_WAKEUP_CFG_SESSVALID_EN BIT(1)
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#define USBSS_WAKEUP_CFG_VBUSVALID_EN BIT(0)
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/* WAKEUP STAT register bits */
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#define USBSS_WAKEUP_STAT_OVERCURRENT BIT(4)
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#define USBSS_WAKEUP_STAT_LINESTATE BIT(3)
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#define USBSS_WAKEUP_STAT_SESSVALID BIT(2)
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#define USBSS_WAKEUP_STAT_VBUSVALID BIT(1)
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#define USBSS_WAKEUP_STAT_CLR BIT(0)
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/* IRQ_MISC_STATUS_RAW register bits */
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#define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22)
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#define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20)
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/* IRQ_MISC_STATUS register bits */
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#define USBSS_IRQ_MISC_VBUSVALID BIT(22)
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#define USBSS_IRQ_MISC_SESSVALID BIT(20)
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/* IRQ_MISC_ENABLE_SET register bits */
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#define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID BIT(22)
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#define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID BIT(20)
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/* IRQ_MISC_ENABLE_CLR register bits */
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#define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID BIT(22)
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#define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID BIT(20)
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/* IRQ_MISC_EOI register bits */
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#define USBSS_IRQ_MISC_EOI_VECTOR BIT(0)
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/* VBUS_STAT register bits */
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#define USBSS_VBUS_STAT_SESSVALID BIT(2)
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#define USBSS_VBUS_STAT_VBUSVALID BIT(0)
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/* Mask for PHY PLL REFCLK */
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#define PHY_PLL_REFCLK_MASK GENMASK(3, 0)
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#define DWC3_AM62_AUTOSUSPEND_DELAY 100
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struct dwc3_data {
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struct device *dev;
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void __iomem *usbss;
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struct clk *usb2_refclk;
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int rate_code;
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struct regmap *syscon;
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unsigned int offset;
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unsigned int vbus_divider;
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};
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static const int dwc3_ti_rate_table[] = { /* in KHZ */
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9600,
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10000,
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12000,
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19200,
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20000,
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24000,
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25000,
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26000,
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38400,
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40000,
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58000,
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50000,
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52000,
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};
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static inline u32 dwc3_ti_readl(struct dwc3_data *data, u32 offset)
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{
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return readl((data->usbss) + offset);
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}
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static inline void dwc3_ti_writel(struct dwc3_data *data, u32 offset, u32 value)
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{
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writel(value, (data->usbss) + offset);
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}
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static int phy_syscon_pll_refclk(struct dwc3_data *data)
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{
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struct device *dev = data->dev;
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struct device_node *node = dev->of_node;
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struct of_phandle_args args;
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struct regmap *syscon;
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int ret;
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syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-phy-pll-refclk");
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if (IS_ERR(syscon)) {
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dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n");
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return PTR_ERR(syscon);
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}
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data->syscon = syscon;
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ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-phy-pll-refclk", 1,
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0, &args);
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if (ret)
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return ret;
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data->offset = args.args[0];
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ret = regmap_update_bits(data->syscon, data->offset, PHY_PLL_REFCLK_MASK, data->rate_code);
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if (ret) {
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dev_err(dev, "failed to set phy pll reference clock rate\n");
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return ret;
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}
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return 0;
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}
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static int dwc3_ti_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct dwc3_data *data;
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int i, ret;
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unsigned long rate;
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u32 reg;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->dev = dev;
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platform_set_drvdata(pdev, data);
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data->usbss = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->usbss)) {
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dev_err(dev, "can't map IOMEM resource\n");
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return PTR_ERR(data->usbss);
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}
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data->usb2_refclk = devm_clk_get(dev, "ref");
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if (IS_ERR(data->usb2_refclk)) {
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dev_err(dev, "can't get usb2_refclk\n");
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return PTR_ERR(data->usb2_refclk);
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}
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/* Calculate the rate code */
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rate = clk_get_rate(data->usb2_refclk);
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rate /= 1000; // To KHz
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for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) {
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if (dwc3_ti_rate_table[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(dwc3_ti_rate_table)) {
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dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
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ret = -EINVAL;
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goto err_clk_disable;
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}
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data->rate_code = i;
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/* Read the syscon property and set the rate code */
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ret = phy_syscon_pll_refclk(data);
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if (ret)
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goto err_clk_disable;
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/* VBUS divider select */
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data->vbus_divider = device_property_read_bool(dev, "ti,vbus-divider");
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reg = dwc3_ti_readl(data, USBSS_PHY_CONFIG);
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if (data->vbus_divider)
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reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT;
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dwc3_ti_writel(data, USBSS_PHY_CONFIG, reg);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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/*
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* Don't ignore its dependencies with its children
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*/
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pm_suspend_ignore_children(dev, false);
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clk_prepare_enable(data->usb2_refclk);
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pm_runtime_get_noresume(dev);
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ret = of_platform_populate(node, NULL, NULL, dev);
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if (ret) {
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dev_err(dev, "failed to create dwc3 core: %d\n", ret);
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goto err_pm_disable;
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}
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/* Set mode valid bit to indicate role is valid */
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reg = dwc3_ti_readl(data, USBSS_MODE_CONTROL);
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reg |= USBSS_MODE_VALID;
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dwc3_ti_writel(data, USBSS_MODE_CONTROL, reg);
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/* Setting up autosuspend */
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pm_runtime_set_autosuspend_delay(dev, DWC3_AM62_AUTOSUSPEND_DELAY);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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err_pm_disable:
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clk_disable_unprepare(data->usb2_refclk);
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pm_runtime_disable(dev);
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pm_runtime_set_suspended(dev);
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err_clk_disable:
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clk_put(data->usb2_refclk);
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return ret;
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}
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static int dwc3_ti_remove_core(struct device *dev, void *c)
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{
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struct platform_device *pdev = to_platform_device(dev);
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platform_device_unregister(pdev);
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return 0;
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}
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static int dwc3_ti_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dwc3_data *data = platform_get_drvdata(pdev);
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u32 reg;
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device_for_each_child(dev, NULL, dwc3_ti_remove_core);
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/* Clear mode valid bit */
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reg = dwc3_ti_readl(data, USBSS_MODE_CONTROL);
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reg &= ~USBSS_MODE_VALID;
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dwc3_ti_writel(data, USBSS_MODE_CONTROL, reg);
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pm_runtime_put_sync(dev);
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clk_disable_unprepare(data->usb2_refclk);
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pm_runtime_disable(dev);
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pm_runtime_set_suspended(dev);
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clk_put(data->usb2_refclk);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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#ifdef CONFIG_PM
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static int dwc3_ti_suspend_common(struct device *dev)
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{
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struct dwc3_data *data = dev_get_drvdata(dev);
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clk_disable_unprepare(data->usb2_refclk);
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return 0;
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}
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static int dwc3_ti_resume_common(struct device *dev)
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{
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struct dwc3_data *data = dev_get_drvdata(dev);
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clk_prepare_enable(data->usb2_refclk);
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return 0;
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}
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static UNIVERSAL_DEV_PM_OPS(dwc3_ti_pm_ops, dwc3_ti_suspend_common,
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dwc3_ti_resume_common, NULL);
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#define DEV_PM_OPS (&dwc3_ti_pm_ops)
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#else
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#define DEV_PM_OPS NULL
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#endif /* CONFIG_PM */
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static const struct of_device_id dwc3_ti_of_match[] = {
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{ .compatible = "ti,am62-usb"},
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{},
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};
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MODULE_DEVICE_TABLE(of, dwc3_ti_of_match);
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static struct platform_driver dwc3_ti_driver = {
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.probe = dwc3_ti_probe,
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.remove = dwc3_ti_remove,
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.driver = {
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.name = "dwc3-am62",
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.pm = DEV_PM_OPS,
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.of_match_table = dwc3_ti_of_match,
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},
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};
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module_platform_driver(dwc3_ti_driver);
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MODULE_ALIAS("platform:dwc3-am62");
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MODULE_AUTHOR("Aswath Govindraju <a-govindraju@ti.com>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("DesignWare USB3 TI Glue Layer");
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