Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM/arm64 Devicetree updates from Olof Johansson:
"As usual, device tree updates is the bulk of our material in this
merge window. This time around, 559 patches affecting both 32- and
64-bit platforms.
Changes are too many to list individually, but some of the larger
ones:
New platform/SoC support:
- Automotive:
+ Renesas R-Car D3 (R8A77995)
+ TI DT76x
+ MediaTek mt2712e
- Communication-oriented:
+ Qualcomm IPQ8074
+ Broadcom Stingray
+ Marvell Armada 8080
- Set top box:
+ Uniphier PXs3
Besides some vendor reference boards for the SoC above, there are also
several new boards/machines:
- TI AM335x Moxa UC-8100-ME-T open platform
- TI AM57xx Beaglebone X15 Rev C
- Microchip/Atmel sama5d27 SoM1 EK
- Broadcom Raspberry Pi Zero W
- Gemini-based D-Link DIR-685 router
- Freescale i.MX6:
+ Toradex Apalis module + Apalis and Ixora carrier boards
+ Engicam GEAM6UL Starter Kit
- Freescale i.MX53-based Beckhoff CX9020 Embedded PC
- Mediatek mt7623-based BananaPi R2
- Several Allwinner-based single-board computers:
+ Cubietruck plus
+ Bananapi M3, M2M and M64
+ NanoPi A64
+ A64-OLinuXino
+ Pine64
- Rockchip RK3328 Pine64/Rock64 board support
- Rockchip RK3399 boards:
+ RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
+ Theobroma Systems RK3399-Q7 SoM
- ZTE ZX296718 PCBOX Board"
* tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits)
ARM: dts: at91: at91sam9g45: add AC97
arm64: dts: marvell: mcbin: enable more networking ports
arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
arm64: dts: marvell: add TX interrupts for PPv2.2
arm64: dts: uniphier: add PXs3 SoC support
ARM: dts: uniphier: add pinctrl groups of ethernet phy mode
ARM: dts: uniphier: fix size of sdctrl nodes
ARM: dts: uniphier: add AIDET nodes
arm64: dts: uniphier: fix size of sdctrl node
arm64: dts: uniphier: add AIDET nodes
Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2"
arm64: dts: uniphier: add reset controller node of analog amplifier
arm64: dts: marvell: add Device Tree files for Armada-8KP
arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
dt-bindings: add rk3399-q7 SoM
ARM: dts: rockchip: enable usb for rv1108-evb
ARM: dts: rockchip: add usb nodes for rv1108 SoCs
dt-bindings: update grf-binding for rv1108 SoCs
ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
...
This commit is contained in:
Linus Torvalds
@ -62,5 +62,6 @@
|
||||
#define CLKID_AO_UART1 3
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||||
#define CLKID_AO_UART2 4
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||||
#define CLKID_AO_IR_BLASTER 5
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#define CLKID_AO_CEC_32K 6
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#endif
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||||
@ -5,37 +5,96 @@
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||||
#ifndef __GXBB_CLKC_H
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||||
#define __GXBB_CLKC_H
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||||
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||||
#define CLKID_SYS_PLL 0
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||||
#define CLKID_HDMI_PLL 2
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||||
#define CLKID_FIXED_PLL 3
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||||
#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
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#define CLKID_MPLL2 15
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_SMART_CARD 24
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_I2S_SPDIF 35
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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#define CLKID_MIXER_IFACE 44
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_G2D 49
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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#define CLKID_USB 55
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A53 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCI_INT1 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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#define CLKID_AO_I2C 93
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||||
#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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@ -50,5 +109,9 @@
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#define CLKID_CTS_AMCLK 107
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||||
#define CLKID_CTS_MCLK_I958 110
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#define CLKID_CTS_I958 113
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#define CLKID_32K_CLK 114
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#define CLKID_SD_EMMC_A_CLK0 119
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#define CLKID_SD_EMMC_B_CLK0 122
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#define CLKID_SD_EMMC_C_CLK0 125
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||||
#endif /* __GXBB_CLKC_H */
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|
||||
@ -21,15 +21,85 @@
|
||||
#define CLKID_ZERO 13
|
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#define CLKID_MPEG_SEL 14
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#define CLKID_MPEG_DIV 15
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
|
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#define CLKID_PL301 19
|
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
|
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#define CLKID_I2C 22
|
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#define CLKID_SAR_ADC 23
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#define CLKID_SMART_CARD 24
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||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
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||||
#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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#define CLKID_SPI 34
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#define CLKID_I2S_SPDIF 35
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#define CLKID_ETH 36
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
|
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
|
||||
#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
|
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#define CLKID_MIXER_IFACE 44
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
|
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#define CLKID_AIU 47
|
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#define CLKID_UART1 48
|
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#define CLKID_G2D 49
|
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#define CLKID_USB0 50
|
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#define CLKID_USB1 51
|
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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||||
#define CLKID_DOS_PARSER 54
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#define CLKID_USB 55
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A9 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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#define CLKID_GCLK_VENCI_INT 77
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#define CLKID_GCLK_VENCP_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCL_INT 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK2_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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#define CLKID_MPLL0 93
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#define CLKID_MPLL1 94
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#define CLKID_MPLL2 95
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#endif /* __MESON8B_CLKC_H */
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@ -43,12 +43,73 @@
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#define SCLK_SDMMC_SAMPLE 84
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#define SCLK_SDIO_SAMPLE 85
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#define SCLK_EMMC_SAMPLE 86
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#define SCLK_VENC_CORE 87
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#define SCLK_HEVC_CORE 88
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#define SCLK_HEVC_CABAC 89
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#define SCLK_PWM0_PMU 90
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#define SCLK_I2C0_PMU 91
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#define SCLK_WIFI 92
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#define SCLK_CIFOUT 93
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#define SCLK_MIPI_CSI_OUT 94
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#define SCLK_CIF0 95
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#define SCLK_CIF1 96
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#define SCLK_CIF2 97
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#define SCLK_CIF3 98
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#define SCLK_DSP 99
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#define SCLK_DSP_IOP 100
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#define SCLK_DSP_EPP 101
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#define SCLK_DSP_EDP 102
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#define SCLK_DSP_EDAP 103
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#define SCLK_CVBS_HOST 104
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#define SCLK_HDMI_SFR 105
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#define SCLK_HDMI_CEC 106
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#define SCLK_CRYPTO 107
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#define SCLK_SPI 108
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#define SCLK_SARADC 109
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#define SCLK_TSADC 110
|
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#define SCLK_MACPHY_PRE 111
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#define SCLK_MACPHY 112
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#define SCLK_MACPHY_RX 113
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#define SCLK_MAC_REF 114
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#define SCLK_MAC_REFOUT 115
|
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#define SCLK_DSP_PFM 116
|
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#define SCLK_RGA 117
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#define SCLK_I2C1 118
|
||||
#define SCLK_I2C2 119
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||||
#define SCLK_I2C3 120
|
||||
#define SCLK_PWM 121
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#define SCLK_ISP 122
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#define SCLK_USBPHY 123
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#define SCLK_I2S0_SRC 124
|
||||
#define SCLK_I2S1_SRC 125
|
||||
#define SCLK_I2S2_SRC 126
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#define SCLK_UART0_SRC 127
|
||||
#define SCLK_UART1_SRC 128
|
||||
#define SCLK_UART2_SRC 129
|
||||
|
||||
#define DCLK_VOP_SRC 185
|
||||
#define DCLK_HDMIPHY 186
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||||
#define DCLK_VOP 187
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||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 192
|
||||
#define ACLK_PRE 193
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||||
#define ACLK_CORE 194
|
||||
#define ACLK_ENMCORE 195
|
||||
#define ACLK_RKVENC 196
|
||||
#define ACLK_RKVDEC 197
|
||||
#define ACLK_VPU 198
|
||||
#define ACLK_CIF0 199
|
||||
#define ACLK_VIO0 200
|
||||
#define ACLK_VIO1 201
|
||||
#define ACLK_VOP 202
|
||||
#define ACLK_IEP 203
|
||||
#define ACLK_RGA 204
|
||||
#define ACLK_ISP 205
|
||||
#define ACLK_CIF1 206
|
||||
#define ACLK_CIF2 207
|
||||
#define ACLK_CIF3 208
|
||||
#define ACLK_PERI 209
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO1 256
|
||||
@ -67,10 +128,23 @@
|
||||
#define PCLK_PWM 269
|
||||
#define PCLK_TIMER 270
|
||||
#define PCLK_PERI 271
|
||||
#define PCLK_GPIO0_PMU 272
|
||||
#define PCLK_I2C0_PMU 273
|
||||
#define PCLK_PWM0_PMU 274
|
||||
#define PCLK_ISP 275
|
||||
#define PCLK_VIO 276
|
||||
#define PCLK_MIPI_DSI 277
|
||||
#define PCLK_HDMI_CTRL 278
|
||||
#define PCLK_SARADC 279
|
||||
#define PCLK_DSP_CFG 280
|
||||
#define PCLK_BUS 281
|
||||
#define PCLK_EFUSE0 282
|
||||
#define PCLK_EFUSE1 283
|
||||
#define PCLK_WDT 284
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 320
|
||||
#define HCLK_I2S1_8CH 321
|
||||
#define HCLK_I2S1_2CH 321
|
||||
#define HCLK_I2S2_2CH 322
|
||||
#define HCLK_NANDC 323
|
||||
#define HCLK_SDMMC 324
|
||||
@ -78,20 +152,37 @@
|
||||
#define HCLK_EMMC 326
|
||||
#define HCLK_PERI 327
|
||||
#define HCLK_SFC 328
|
||||
#define HCLK_RKVENC 329
|
||||
#define HCLK_RKVDEC 330
|
||||
#define HCLK_CIF0 331
|
||||
#define HCLK_VIO 332
|
||||
#define HCLK_VOP 333
|
||||
#define HCLK_IEP 334
|
||||
#define HCLK_RGA 335
|
||||
#define HCLK_ISP 336
|
||||
#define HCLK_CRYPTO_MST 337
|
||||
#define HCLK_CRYPTO_SLV 338
|
||||
#define HCLK_HOST0 339
|
||||
#define HCLK_OTG 340
|
||||
#define HCLK_CIF1 341
|
||||
#define HCLK_CIF2 342
|
||||
#define HCLK_CIF3 343
|
||||
#define HCLK_BUS 344
|
||||
#define HCLK_VPU 345
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_SFC + 1)
|
||||
#define CLK_NR_CLKS (HCLK_VPU + 1)
|
||||
|
||||
/* reset id */
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_AD 1
|
||||
#define SRST_L2_AD 2
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CORE_PO 4
|
||||
#define SRST_CORE 5
|
||||
#define SRST_L2 6
|
||||
#define SRST_L2 6
|
||||
#define SRST_CORE_DBG 8
|
||||
#define PRST_DBG 9
|
||||
#define RST_DAP 10
|
||||
#define RST_DAP 10
|
||||
#define PRST_DBG_NIU 11
|
||||
#define ARST_STRC_SYS_AD 15
|
||||
|
||||
@ -158,9 +249,9 @@
|
||||
#define HRST_SYSBUS 75
|
||||
#define PRST_USBGRF 76
|
||||
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define HRST_PERIPH 83
|
||||
#define HRST_SDMMC 84
|
||||
#define HRST_SDIO 85
|
||||
@ -178,7 +269,7 @@
|
||||
#define HRST_HOST0_AUX 96
|
||||
#define HRST_HOST0_ARB 97
|
||||
#define SRST_HOST0_EHCIPHY 98
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_USBPOR 100
|
||||
#define SRST_UTMI0 101
|
||||
#define SRST_UTMI1 102
|
||||
@ -225,21 +316,21 @@
|
||||
#define HRST_VPU_NIU 141
|
||||
#define ARST_VPU 142
|
||||
#define HRST_VPU 143
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC 146
|
||||
#define HRST_RKVDEC 147
|
||||
#define SRST_RKVDEC_CABAC 148
|
||||
#define SRST_RKVDEC_CORE 149
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC 152
|
||||
#define HRST_RKVENC 153
|
||||
#define SRST_RKVENC_CORE 154
|
||||
|
||||
#define SRST_DSP_CORE 156
|
||||
#define SRST_DSP_SYS 157
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_OECM 159
|
||||
#define PRST_DSP_IOP_NIU 160
|
||||
#define ARST_DSP_EPP_NIU 161
|
||||
@ -257,7 +348,7 @@
|
||||
#define SRST_PMU_I2C0 173
|
||||
#define PRST_PMU_I2C0 174
|
||||
#define PRST_PMU_GPIO0 175
|
||||
#define PRST_PMU_INTMEM 176
|
||||
#define PRST_PMU_INTMEM 176
|
||||
#define PRST_PMU_PWM0 177
|
||||
#define SRST_PMU_PWM0 178
|
||||
#define PRST_PMU_GRF 179
|
||||
|
||||
@ -1,90 +0,0 @@
|
||||
/*
|
||||
* TI K2G SoC Device definitions
|
||||
*
|
||||
* Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GENPD_K2G_H
|
||||
#define _DT_BINDINGS_GENPD_K2G_H
|
||||
|
||||
/* Documented in http://processors.wiki.ti.com/index.php/TISCI */
|
||||
|
||||
#define K2G_DEV_PMMC0 0x0000
|
||||
#define K2G_DEV_MLB0 0x0001
|
||||
#define K2G_DEV_DSS0 0x0002
|
||||
#define K2G_DEV_MCBSP0 0x0003
|
||||
#define K2G_DEV_MCASP0 0x0004
|
||||
#define K2G_DEV_MCASP1 0x0005
|
||||
#define K2G_DEV_MCASP2 0x0006
|
||||
#define K2G_DEV_DCAN0 0x0008
|
||||
#define K2G_DEV_DCAN1 0x0009
|
||||
#define K2G_DEV_EMIF0 0x000a
|
||||
#define K2G_DEV_MMCHS0 0x000b
|
||||
#define K2G_DEV_MMCHS1 0x000c
|
||||
#define K2G_DEV_GPMC0 0x000d
|
||||
#define K2G_DEV_ELM0 0x000e
|
||||
#define K2G_DEV_SPI0 0x0010
|
||||
#define K2G_DEV_SPI1 0x0011
|
||||
#define K2G_DEV_SPI2 0x0012
|
||||
#define K2G_DEV_SPI3 0x0013
|
||||
#define K2G_DEV_ICSS0 0x0014
|
||||
#define K2G_DEV_ICSS1 0x0015
|
||||
#define K2G_DEV_USB0 0x0016
|
||||
#define K2G_DEV_USB1 0x0017
|
||||
#define K2G_DEV_NSS0 0x0018
|
||||
#define K2G_DEV_PCIE0 0x0019
|
||||
#define K2G_DEV_GPIO0 0x001b
|
||||
#define K2G_DEV_GPIO1 0x001c
|
||||
#define K2G_DEV_TIMER64_0 0x001d
|
||||
#define K2G_DEV_TIMER64_1 0x001e
|
||||
#define K2G_DEV_TIMER64_2 0x001f
|
||||
#define K2G_DEV_TIMER64_3 0x0020
|
||||
#define K2G_DEV_TIMER64_4 0x0021
|
||||
#define K2G_DEV_TIMER64_5 0x0022
|
||||
#define K2G_DEV_TIMER64_6 0x0023
|
||||
#define K2G_DEV_MSGMGR0 0x0025
|
||||
#define K2G_DEV_BOOTCFG0 0x0026
|
||||
#define K2G_DEV_ARM_BOOTROM0 0x0027
|
||||
#define K2G_DEV_DSP_BOOTROM0 0x0029
|
||||
#define K2G_DEV_DEBUGSS0 0x002b
|
||||
#define K2G_DEV_UART0 0x002c
|
||||
#define K2G_DEV_UART1 0x002d
|
||||
#define K2G_DEV_UART2 0x002e
|
||||
#define K2G_DEV_EHRPWM0 0x002f
|
||||
#define K2G_DEV_EHRPWM1 0x0030
|
||||
#define K2G_DEV_EHRPWM2 0x0031
|
||||
#define K2G_DEV_EHRPWM3 0x0032
|
||||
#define K2G_DEV_EHRPWM4 0x0033
|
||||
#define K2G_DEV_EHRPWM5 0x0034
|
||||
#define K2G_DEV_EQEP0 0x0035
|
||||
#define K2G_DEV_EQEP1 0x0036
|
||||
#define K2G_DEV_EQEP2 0x0037
|
||||
#define K2G_DEV_ECAP0 0x0038
|
||||
#define K2G_DEV_ECAP1 0x0039
|
||||
#define K2G_DEV_I2C0 0x003a
|
||||
#define K2G_DEV_I2C1 0x003b
|
||||
#define K2G_DEV_I2C2 0x003c
|
||||
#define K2G_DEV_EDMA0 0x003f
|
||||
#define K2G_DEV_SEMAPHORE0 0x0040
|
||||
#define K2G_DEV_INTC0 0x0041
|
||||
#define K2G_DEV_GIC0 0x0042
|
||||
#define K2G_DEV_QSPI0 0x0043
|
||||
#define K2G_DEV_ARM_64B_COUNTER0 0x0044
|
||||
#define K2G_DEV_TETRIS0 0x0045
|
||||
#define K2G_DEV_CGEM0 0x0046
|
||||
#define K2G_DEV_MSMC0 0x0047
|
||||
#define K2G_DEV_CBASS0 0x0049
|
||||
#define K2G_DEV_BOARD0 0x004c
|
||||
#define K2G_DEV_EDMA1 0x004f
|
||||
|
||||
#endif
|
||||
@ -73,5 +73,8 @@
|
||||
*/
|
||||
#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
|
||||
|
||||
/* DRA7 IODELAY configuration parameters */
|
||||
#define A_DELAY_PS(val) ((val) & 0xffff)
|
||||
#define G_DELAY_PS(val) ((val) & 0xffff)
|
||||
#endif
|
||||
|
||||
|
||||
27
include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
Normal file
27
include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
|
||||
|
||||
#define CLKC_RESET_L2_CACHE_SOFT_RESET 0
|
||||
#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
|
||||
#define CLKC_RESET_SCU_SOFT_RESET 2
|
||||
#define CLKC_RESET_CPU0_SOFT_RESET 3
|
||||
#define CLKC_RESET_CPU1_SOFT_RESET 4
|
||||
#define CLKC_RESET_CPU2_SOFT_RESET 5
|
||||
#define CLKC_RESET_CPU3_SOFT_RESET 6
|
||||
#define CLKC_RESET_A5_GLOBAL_RESET 7
|
||||
#define CLKC_RESET_A5_AXI_SOFT_RESET 8
|
||||
#define CLKC_RESET_A5_ABP_SOFT_RESET 9
|
||||
#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
|
||||
#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
|
||||
|
||||
#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
|
||||
Reference in New Issue
Block a user