net: phy: aquantia: add firmware load support
Aquantia PHY-s require firmware to be loaded before they start operating. It can be automatically loaded in case when there is a SPI-NOR connected to Aquantia PHY-s or can be loaded from the host via MDIO. This patch adds support for loading the firmware via MDIO as in most cases there is no SPI-NOR being used to save on cost. Firmware loading code itself is ported from mainline U-boot with cleanups. The firmware has mixed values both in big and little endian. PHY core itself is big-endian but it expects values to be in little-endian. The firmware is little-endian but CRC-16 value for it is stored at the end of firmware in big-endian. It seems the PHY does the conversion internally from firmware that is little-endian to the PHY that is big-endian on using the mailbox but mailbox returns a big-endian CRC-16 to verify the written data integrity. Co-developed-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Robert Marko
David S. Miller
parent
e1fbfa4a99
commit
e93984ebc1
@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config AQUANTIA_PHY
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tristate "Aquantia PHYs"
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select CRC_CCITT
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help
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Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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aquantia-objs += aquantia_main.o
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aquantia-objs += aquantia_main.o aquantia_firmware.o
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ifdef CONFIG_HWMON
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aquantia-objs += aquantia_hwmon.o
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endif
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@ -10,10 +10,35 @@
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#include <linux/phy.h>
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/* Vendor specific 1, MDIO_MMD_VEND1 */
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#define VEND1_GLOBAL_SC 0x0
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#define VEND1_GLOBAL_SC_SOFT_RESET BIT(15)
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#define VEND1_GLOBAL_SC_LOW_POWER BIT(11)
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#define VEND1_GLOBAL_FW_ID 0x0020
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#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
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#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE1 0x0200
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#define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE BIT(15)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE BIT(14)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET BIT(12)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY BIT(8)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE2 0x0201
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#define VEND1_GLOBAL_MAILBOX_INTERFACE3 0x0202
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#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16))
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#define VEND1_GLOBAL_MAILBOX_INTERFACE4 0x0203
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#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK GENMASK(15, 2)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))
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#define VEND1_GLOBAL_MAILBOX_INTERFACE5 0x0204
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#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16))
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#define VEND1_GLOBAL_MAILBOX_INTERFACE6 0x0205
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#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0)
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#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))
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/* The following registers all have similar layouts; first the registers... */
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#define VEND1_GLOBAL_CFG_10M 0x0310
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#define VEND1_GLOBAL_CFG_100M 0x031b
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@ -28,6 +53,11 @@
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#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
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/* Vendor specific 1, MDIO_MMD_VEND2 */
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#define VEND1_GLOBAL_CONTROL2 0xc001
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#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST BIT(15)
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#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD BIT(6)
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#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL BIT(0)
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#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
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#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
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#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
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@ -83,3 +113,5 @@ int aqr_hwmon_probe(struct phy_device *phydev);
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#else
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static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
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#endif
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int aqr_firmware_load(struct phy_device *phydev);
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370
drivers/net/phy/aquantia/aquantia_firmware.c
Normal file
370
drivers/net/phy/aquantia/aquantia_firmware.c
Normal file
@ -0,0 +1,370 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/bitfield.h>
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#include <linux/of.h>
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#include <linux/firmware.h>
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#include <linux/crc-ccitt.h>
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#include <linux/nvmem-consumer.h>
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#include <asm/unaligned.h>
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#include "aquantia.h"
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#define UP_RESET_SLEEP 100
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/* addresses of memory segments in the phy */
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#define DRAM_BASE_ADDR 0x3FFE0000
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#define IRAM_BASE_ADDR 0x40000000
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/* firmware image format constants */
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#define VERSION_STRING_SIZE 0x40
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#define VERSION_STRING_OFFSET 0x0200
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/* primary offset is written at an offset from the start of the fw blob */
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#define PRIMARY_OFFSET_OFFSET 0x8
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/* primary offset needs to be then added to a base offset */
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#define PRIMARY_OFFSET_SHIFT 12
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#define PRIMARY_OFFSET(x) ((x) << PRIMARY_OFFSET_SHIFT)
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#define HEADER_OFFSET 0x300
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struct aqr_fw_header {
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u32 padding;
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u8 iram_offset[3];
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u8 iram_size[3];
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u8 dram_offset[3];
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u8 dram_size[3];
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} __packed;
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enum aqr_fw_src {
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AQR_FW_SRC_NVMEM = 0,
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AQR_FW_SRC_FS,
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};
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static const char * const aqr_fw_src_string[] = {
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[AQR_FW_SRC_NVMEM] = "NVMEM",
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[AQR_FW_SRC_FS] = "FS",
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};
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/* AQR firmware doesn't have fixed offsets for iram and dram section
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* but instead provide an header with the offset to use on reading
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* and parsing the firmware.
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*
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* AQR firmware can't be trusted and each offset is validated to be
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* not negative and be in the size of the firmware itself.
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*/
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static bool aqr_fw_validate_get(size_t size, size_t offset, size_t get_size)
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{
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return offset + get_size <= size;
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}
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static int aqr_fw_get_be16(const u8 *data, size_t offset, size_t size, u16 *value)
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{
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if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
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return -EINVAL;
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*value = get_unaligned_be16(data + offset);
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return 0;
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}
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static int aqr_fw_get_le16(const u8 *data, size_t offset, size_t size, u16 *value)
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{
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if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
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return -EINVAL;
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*value = get_unaligned_le16(data + offset);
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return 0;
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}
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static int aqr_fw_get_le24(const u8 *data, size_t offset, size_t size, u32 *value)
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{
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if (!aqr_fw_validate_get(size, offset, sizeof(u8) * 3))
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return -EINVAL;
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*value = get_unaligned_le24(data + offset);
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return 0;
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}
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/* load data into the phy's memory */
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static int aqr_fw_load_memory(struct phy_device *phydev, u32 addr,
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const u8 *data, size_t len)
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{
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u16 crc = 0, up_crc;
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size_t pos;
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/* PHY expect addr in LE */
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addr = (__force u32)cpu_to_le32(addr);
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phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_MAILBOX_INTERFACE1,
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VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
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phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_MAILBOX_INTERFACE3,
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VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(addr));
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phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_MAILBOX_INTERFACE4,
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VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(addr));
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/* We assume and enforce the size to be word aligned.
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* If a firmware that is not word aligned is found, please report upstream.
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*/
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for (pos = 0; pos < len; pos += sizeof(u32)) {
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u32 word;
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/* FW data is always stored in little-endian */
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word = get_unaligned((const u32 *)(data + pos));
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
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VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,
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VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(word));
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,
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VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
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VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
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/* calculate CRC as we load data to the mailbox.
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* We convert word to big-endian as PHY is BE and mailbox will
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* return a BE CRC.
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*/
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word = (__force u32)cpu_to_be32(word);
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crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
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}
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up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
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if (crc != up_crc) {
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phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
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crc, up_crc);
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return -EINVAL;
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}
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return 0;
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}
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static int aqr_fw_boot(struct phy_device *phydev, const u8 *data, size_t size,
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enum aqr_fw_src fw_src)
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{
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u16 calculated_crc, read_crc, read_primary_offset;
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u32 iram_offset = 0, iram_size = 0;
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u32 dram_offset = 0, dram_size = 0;
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char version[VERSION_STRING_SIZE];
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u32 primary_offset = 0;
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int ret;
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/* extract saved CRC at the end of the fw
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* CRC is saved in big-endian as PHY is BE
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*/
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ret = aqr_fw_get_be16(data, size - sizeof(u16), size, &read_crc);
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if (ret) {
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phydev_err(phydev, "bad firmware CRC in firmware\n");
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return ret;
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}
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calculated_crc = crc_ccitt_false(0, data, size - sizeof(u16));
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if (read_crc != calculated_crc) {
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phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n",
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read_crc, calculated_crc);
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return -EINVAL;
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}
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/* Get the primary offset to extract DRAM and IRAM sections. */
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ret = aqr_fw_get_le16(data, PRIMARY_OFFSET_OFFSET, size, &read_primary_offset);
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if (ret) {
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phydev_err(phydev, "bad primary offset in firmware\n");
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return ret;
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}
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primary_offset = PRIMARY_OFFSET(read_primary_offset);
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/* Find the DRAM and IRAM sections within the firmware file.
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* Make sure the fw_header is correctly in the firmware.
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*/
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if (!aqr_fw_validate_get(size, primary_offset + HEADER_OFFSET,
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sizeof(struct aqr_fw_header))) {
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phydev_err(phydev, "bad fw_header in firmware\n");
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return -EINVAL;
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}
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/* offset are in LE and values needs to be converted to cpu endian */
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ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
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offsetof(struct aqr_fw_header, iram_offset),
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size, &iram_offset);
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if (ret) {
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phydev_err(phydev, "bad iram offset in firmware\n");
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return ret;
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}
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ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
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offsetof(struct aqr_fw_header, iram_size),
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size, &iram_size);
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if (ret) {
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phydev_err(phydev, "invalid iram size in firmware\n");
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return ret;
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}
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ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
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offsetof(struct aqr_fw_header, dram_offset),
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size, &dram_offset);
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if (ret) {
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phydev_err(phydev, "bad dram offset in firmware\n");
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return ret;
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}
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ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
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offsetof(struct aqr_fw_header, dram_size),
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size, &dram_size);
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if (ret) {
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phydev_err(phydev, "invalid dram size in firmware\n");
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return ret;
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}
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/* Increment the offset with the primary offset.
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* Validate iram/dram offset and size.
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*/
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iram_offset += primary_offset;
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if (iram_size % sizeof(u32)) {
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phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n");
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return -EINVAL;
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}
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if (!aqr_fw_validate_get(size, iram_offset, iram_size)) {
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phydev_err(phydev, "invalid iram offset for iram size\n");
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return -EINVAL;
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}
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dram_offset += primary_offset;
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if (dram_size % sizeof(u32)) {
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phydev_err(phydev, "dram size if not aligned to word size. Please report this upstream!\n");
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return -EINVAL;
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}
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if (!aqr_fw_validate_get(size, dram_offset, dram_size)) {
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phydev_err(phydev, "invalid iram offset for iram size\n");
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return -EINVAL;
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}
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phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n",
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primary_offset, iram_offset, iram_size, dram_offset, dram_size);
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if (!aqr_fw_validate_get(size, dram_offset + VERSION_STRING_OFFSET,
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VERSION_STRING_SIZE)) {
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phydev_err(phydev, "invalid version in firmware\n");
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return -EINVAL;
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}
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strscpy(version, (char *)data + dram_offset + VERSION_STRING_OFFSET,
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VERSION_STRING_SIZE);
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if (version[0] == '\0') {
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phydev_err(phydev, "invalid version in firmware\n");
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return -EINVAL;
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}
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phydev_info(phydev, "loading firmware version '%s' from '%s'\n", version,
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aqr_fw_src_string[fw_src]);
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/* stall the microcprocessor */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
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VEND1_GLOBAL_CONTROL2_UP_RUN_STALL | VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
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phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n",
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DRAM_BASE_ADDR, dram_offset, dram_size);
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ret = aqr_fw_load_memory(phydev, DRAM_BASE_ADDR, data + dram_offset,
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dram_size);
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if (ret)
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return ret;
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phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n",
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IRAM_BASE_ADDR, iram_offset, iram_size);
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ret = aqr_fw_load_memory(phydev, IRAM_BASE_ADDR, data + iram_offset,
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iram_size);
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if (ret)
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return ret;
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/* make sure soft reset and low power mode are clear */
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
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VEND1_GLOBAL_SC_SOFT_RESET | VEND1_GLOBAL_SC_LOW_POWER);
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/* Release the microprocessor. UP_RESET must be held for 100 usec. */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
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VEND1_GLOBAL_CONTROL2_UP_RUN_STALL |
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VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD |
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VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST);
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usleep_range(UP_RESET_SLEEP, UP_RESET_SLEEP * 2);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
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VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
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return 0;
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}
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static int aqr_firmware_load_nvmem(struct phy_device *phydev)
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{
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struct nvmem_cell *cell;
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size_t size;
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u8 *buf;
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int ret;
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cell = nvmem_cell_get(&phydev->mdio.dev, "firmware");
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if (IS_ERR(cell))
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return PTR_ERR(cell);
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buf = nvmem_cell_read(cell, &size);
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if (IS_ERR(buf)) {
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ret = PTR_ERR(buf);
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goto exit;
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}
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ret = aqr_fw_boot(phydev, buf, size, AQR_FW_SRC_NVMEM);
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if (ret)
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phydev_err(phydev, "firmware loading failed: %d\n", ret);
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|
||||
kfree(buf);
|
||||
exit:
|
||||
nvmem_cell_put(cell);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int aqr_firmware_load_fs(struct phy_device *phydev)
|
||||
{
|
||||
struct device *dev = &phydev->mdio.dev;
|
||||
const struct firmware *fw;
|
||||
const char *fw_name;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_string(dev->of_node, "firmware-name",
|
||||
&fw_name);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = request_firmware(&fw, fw_name, dev);
|
||||
if (ret) {
|
||||
phydev_err(phydev, "failed to find FW file %s (%d)\n",
|
||||
fw_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = aqr_fw_boot(phydev, fw->data, fw->size, AQR_FW_SRC_FS);
|
||||
if (ret)
|
||||
phydev_err(phydev, "firmware loading failed: %d\n", ret);
|
||||
|
||||
release_firmware(fw);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int aqr_firmware_load(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Check if the firmware is not already loaded by pooling
|
||||
* the current version returned by the PHY. If 0 is returned,
|
||||
* no firmware is loaded.
|
||||
*/
|
||||
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
|
||||
if (ret > 0)
|
||||
goto exit;
|
||||
|
||||
ret = aqr_firmware_load_nvmem(phydev);
|
||||
if (!ret)
|
||||
goto exit;
|
||||
|
||||
ret = aqr_firmware_load_fs(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
exit:
|
||||
return 0;
|
||||
}
|
||||
@ -658,11 +658,17 @@ static int aqr107_resume(struct phy_device *phydev)
|
||||
|
||||
static int aqr107_probe(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
phydev->priv = devm_kzalloc(&phydev->mdio.dev,
|
||||
sizeof(struct aqr107_priv), GFP_KERNEL);
|
||||
if (!phydev->priv)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = aqr_firmware_load(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return aqr_hwmon_probe(phydev);
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user