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clk: renesas: r9a07g044: Rename divider table

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As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
can be reused.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-06-26 09:13:36 +01:00 committed by Geert Uytterhoeven
parent 2fa9fd69b3
commit e93c137361
1 changed files with 4 additions and 3 deletions
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7
drivers/clk/renesas/r9a07g044-cpg.c
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@ -42,12 +42,13 @@ enum clk_ids {
}; };
/* Divider tables */ /* Divider tables */
static const struct clk_div_table dtable_3b[] = { static const struct clk_div_table dtable_1_32[] = {
{0, 1}, {0, 1},
{1, 2}, {1, 2},
{2, 4}, {2, 4},
{3, 8}, {3, 8},
{4, 32}, {4, 32},
{0, 0},
}; };
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@ -72,10 +73,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* Core output clk */ /* Core output clk */
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
dtable_3b, CLK_DIVIDER_HIWORD_MASK), dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
}; };
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {