drm/amd/pm: add SMU11 common gfx ulv control interface
Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -274,5 +274,8 @@ int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
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void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
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int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
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bool enablement);
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#endif
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#endif
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@ -2391,6 +2391,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
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.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
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.get_gpu_metrics = arcturus_get_gpu_metrics,
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.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
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};
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void arcturus_set_ppt_funcs(struct smu_context *smu)
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@ -2660,6 +2660,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
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.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
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.get_gpu_metrics = navi10_get_gpu_metrics,
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.enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
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.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
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};
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void navi10_set_ppt_funcs(struct smu_context *smu)
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@ -2796,6 +2796,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
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.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
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.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
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.enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
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.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
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};
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void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
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@ -1985,3 +1985,14 @@ void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
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gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
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}
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int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
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bool enablement)
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{
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int ret = 0;
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
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return ret;
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}
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