iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

V4L/DVB (11057): Fix CiMax stability in Netup Dual DVB-S2 CI

Browse Source 
It appears TS discontinuity about one per 10 hrs if CAM used.
Patch to fix it.

Signed-off-by: Abylay Ospan <aospan@netup.ru>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Abylay Ospan 2009-03-17 18:21:18 -03:00 committed by Mauro Carvalho Chehab
parent f1bee69944
commit e9d4a6d5ef
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/media/dvb/frontends/stv0900_core.c
View File

@ -250,7 +250,7 @@ enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
} }
msleep(3); msleep(3);
for (i = 0; i < 180; i++) for (i = 0; i < 182; i++)
stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]); stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) { if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {

4
drivers/media/dvb/frontends/stv0900_init.h
View File

@ -217,7 +217,7 @@ static const struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoo
{ STV0900_32APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B, 0x1E, 0x3A, 0x3D, 0x2A, 0x2D } { STV0900_32APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B, 0x1E, 0x3A, 0x3D, 0x2A, 0x2D }
}; };
static const u16 STV0900_InitVal[180][2] = { static const u16 STV0900_InitVal[182][2] = {
{ R0900_OUTCFG , 0x00 }, { R0900_OUTCFG , 0x00 },
{ R0900_MODECFG , 0xff }, { R0900_MODECFG , 0xff },
{ R0900_AGCRF1CFG , 0x11 }, { R0900_AGCRF1CFG , 0x11 },
@ -396,6 +396,8 @@ static const u16 STV0900_InitVal[180][2] = {
{ R0900_DATA72CFG , 0x52 }, { R0900_DATA72CFG , 0x52 },
{ R0900_P1_TSCFGM , 0xc0 }, { R0900_P1_TSCFGM , 0xc0 },
{ R0900_P2_TSCFGM , 0xc0 }, { R0900_P2_TSCFGM , 0xc0 },
{ R0900_P1_TSCFGH , 0xe0 }, /* DVB-CI timings */
{ R0900_P2_TSCFGH , 0xe0 }, /* DVB-CI timings */
{ R0900_P1_TSSPEED , 0x40 }, { R0900_P1_TSSPEED , 0x40 },
{ R0900_P2_TSSPEED , 0x40 }, { R0900_P2_TSSPEED , 0x40 },
}; };