Staging: remove sxg driver
Unfortunatly, the upstream company has abandonded development of this driver. So it's best to just remove the driver from the tree. Cc: Christopher Harrer <charrer@alacritech.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman
parent
0b33559a1a
commit
e9d599220b
@ -45,8 +45,6 @@ source "drivers/staging/et131x/Kconfig"
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source "drivers/staging/slicoss/Kconfig"
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source "drivers/staging/slicoss/Kconfig"
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source "drivers/staging/sxg/Kconfig"
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source "drivers/staging/go7007/Kconfig"
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source "drivers/staging/go7007/Kconfig"
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source "drivers/staging/usbip/Kconfig"
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source "drivers/staging/usbip/Kconfig"
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@ -5,7 +5,6 @@ obj-$(CONFIG_STAGING) += staging.o
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obj-$(CONFIG_ET131X) += et131x/
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obj-$(CONFIG_ET131X) += et131x/
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obj-$(CONFIG_SLICOSS) += slicoss/
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obj-$(CONFIG_SLICOSS) += slicoss/
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obj-$(CONFIG_SXG) += sxg/
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obj-$(CONFIG_VIDEO_GO7007) += go7007/
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obj-$(CONFIG_VIDEO_GO7007) += go7007/
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obj-$(CONFIG_USB_IP_COMMON) += usbip/
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obj-$(CONFIG_USB_IP_COMMON) += usbip/
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obj-$(CONFIG_W35UND) += winbond/
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obj-$(CONFIG_W35UND) += winbond/
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@ -1,11 +0,0 @@
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config SXG
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tristate "Alacritech SLIC Technology Non-Accelerated 10Gbe support"
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depends on PCI && NETDEV_10000
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depends on X86
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default n
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help
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This driver supports the Alacritech SLIC Technology Non-Accelerated
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10Gbe network cards.
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To compile this driver as a module, choose
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M here: the module will be called sxg_nic.
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@ -1,3 +0,0 @@
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obj-$(CONFIG_SXG) += sxg_nic.o
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sxg_nic-y := sxg.o sxg_ethtool.o
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@ -1,12 +0,0 @@
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This is the rough cut at a driver for the Alacritech SLIC Technology
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Non-Accelerated 10Gbe network driver.
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TODO:
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- remove wrappers
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- checkpatch.pl cleanups
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- new functionality that the card needs
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- remove reliance on x86
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Please send patches to:
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Greg Kroah-Hartman <gregkh@suse.de>
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for any cleanups that you do to this driver.
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File diff suppressed because it is too large
Load Diff
@ -1,787 +0,0 @@
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/**************************************************************************
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*
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* Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
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*
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* $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of Alacritech, Inc.
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*
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**************************************************************************/
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/*
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* FILENAME: sxg.h
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*
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* This is the base set of header definitions for the SXG driver.
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*/
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#ifndef __SXG_DRIVER_H__
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#define __SXG_DRIVER_H__
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#define SLIC_DUMP_ENABLED 0
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#define SXG_DRV_NAME "sxg" /* TBD: This might be removed eventually */
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#define SXG_DRV_VERSION "1.0.1"
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extern char sxg_driver_name[];
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#define SXG_NETDEV_WEIGHT 64
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/*
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* struct sxg_stats - Probably move these to someplace where
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* the slicstat (sxgstat?) program can get them.
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*/
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struct sxg_stats {
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/* Xmt */
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u64 DumbXmtUcastPkts; /* directed packets */
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u64 DumbXmtMcastPkts; /* Multicast packets */
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u64 DumbXmtBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
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u64 DumbXmtUcastBytes; /* OID_GEN_DIRECTED_BYTES_XMIT */
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u64 DumbXmtMcastBytes; /* OID_GEN_MULTICAST_BYTES_XMIT */
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u64 DumbXmtBcastBytes; /* OID_GEN_BROADCAST_BYTES_XMIT */
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u64 XmtQLen; /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
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u64 XmtZeroFull; /* Transmit ring zero full */
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/* Rcv */
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u64 DumbRcvUcastBytes; /* OID_GEN_DIRECTED_BYTES_RCV */
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u64 DumbRcvMcastBytes; /* OID_GEN_MULTICAST_BYTES_RCV */
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u64 DumbRcvBcastBytes; /* OID_GEN_BROADCAST_BYTES_RCV */
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u64 DumbRcvUcastPkts; /* directed packets */
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u64 DumbRcvMcastPkts; /* Multicast packets */
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u64 DumbRcvBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
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u64 PdqFull; /* Processed Data Queue Full */
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u64 EventRingFull; /* Event ring full */
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/* Verbose stats */
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u64 NoSglBuf; /* SGL buffer allocation failure */
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u64 NoMem; /* Memory allocation failure */
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u64 NumInts; /* Interrupts */
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u64 FalseInts; /* Interrupt with ISR == 0 */
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/* Sahara receive status */
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u64 TransportCsum; /* SXG_RCV_STATUS_TRANSPORT_CSUM */
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u64 TransportUflow; /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
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u64 TransportHdrLen; /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
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u64 NetworkCsum; /* SXG_RCV_STATUS_NETWORK_CSUM: */
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u64 NetworkUflow; /* SXG_RCV_STATUS_NETWORK_UFLOW: */
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u64 NetworkHdrLen; /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
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u64 Parity; /* SXG_RCV_STATUS_PARITY */
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u64 LinkParity; /* SXG_RCV_STATUS_LINK_PARITY: */
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u64 LinkEarly; /* SXG_RCV_STATUS_LINK_EARLY: */
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u64 LinkBufOflow; /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
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u64 LinkCode; /* SXG_RCV_STATUS_LINK_CODE: */
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u64 LinkDribble; /* SXG_RCV_STATUS_LINK_DRIBBLE: */
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u64 LinkCrc; /* SXG_RCV_STATUS_LINK_CRC: */
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u64 LinkOflow; /* SXG_RCV_STATUS_LINK_OFLOW: */
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u64 LinkUflow; /* SXG_RCV_STATUS_LINK_UFLOW: */
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};
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/* DUMB-NIC Send path definitions */
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#define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb, _phys_addr, _size) { \
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ASSERT(_skb); \
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pci_unmap_single(_pAdapt->pcidev, _size, _phys_addr, PCI_DMA_TODEVICE); \
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dev_kfree_skb_irq(_skb); \
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}
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#define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
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ASSERT(_skb); \
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}
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/*
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* Locate current receive header buffer location. Use this
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* instead of RcvDataHdr->VirtualAddress since the data
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* may have been offset by SXG_ADVANCE_MDL_OFFSET
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*/
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#define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
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/* Dumb-NIC receive processing */
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/* Define an SXG_PACKET as an NDIS_PACKET */
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#define PSXG_PACKET struct sk_buff *
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/* Indications array size */
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#define SXG_RCV_ARRAYSIZE 64
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#define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr, BufferSize) {\
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struct sk_buff * skb; \
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skb = netdev_alloc_skb(_pAdapt->netdev, BufferSize); \
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if (skb) { \
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(_RcvDataBufferHdr)->skb = skb; \
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skb->next = NULL; \
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_RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,\
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_RcvDataBufferHdr->skb->data, BufferSize, PCI_DMA_FROMDEVICE); \
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if (SXG_INVALID_SGL(_RcvDataBufferHdr->PhysicalAddress,BufferSize)) \
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printk(KERN_EMERG "SXG_ALLOCATE_RCV_PACKET: RCV packet" \
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"non-64k boundary aligned\n"); \
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} else { \
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(_RcvDataBufferHdr)->skb = NULL; \
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} \
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}
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#define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
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if((_RcvDataBufferHdr)->skb) { \
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dev_kfree_skb((_RcvDataBufferHdr)->skb); \
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} \
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}
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/*
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* Macro to add a NDIS_PACKET to an indication array
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* If we fill up our array of packet pointers, then indicate this
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* block up now and start on a new one.
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*/
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#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
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_NumPackets) { \
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(_IndicationList)[_NumPackets] = (_Packet); \
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(_NumPackets)++; \
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if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
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(_NumPackets), 0, 0, 0); \
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netif_rx((_IndicationList),(_NumPackets)); \
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(_NumPackets) = 0; \
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} \
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}
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#define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
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if(_NumPackets) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
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(_NumPackets), 0, 0, 0); \
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netif_rx((_IndicationList),(_NumPackets)); \
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(_NumPackets) = 0; \
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} \
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}
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#define SXG_REINIATIALIZE_PACKET(_Packet) \
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{} /*_NdisReinitializePacket(_Packet)*/
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/* this is not necessary with an skb */
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/* Definitions to initialize Dumb-nic Receive NBLs */
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#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
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((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
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#define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
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NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), \
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TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
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#define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
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NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
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NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
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NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
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}
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#define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
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NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
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_Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
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_Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
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NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
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_Packet8021qInfo.Value; \
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}
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#define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
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(_RcvDataBufferHdr), (_Packet), \
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(_Event)->Status, 0); \
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/* ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); */ \
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skb_put(Packet, (_Event)->Length); \
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}
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/*
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* Macros to free a receive data buffer and receive data descriptor block
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* NOTE - Lock must be held with RCV macros
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*/
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#define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
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struct list_entry *_ple; \
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_Hdr = NULL; \
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if((_pAdapt)->FreeRcvBufferCount) { \
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ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
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_ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
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(_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr, \
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FreeList); \
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(_pAdapt)->FreeRcvBufferCount--; \
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ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
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} \
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}
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#define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
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(_Hdr), (_pAdapt)->FreeRcvBufferCount, \
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(_Hdr)->State, 0/*(_Hdr)->VirtualAddress*/); \
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/* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
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(_pAdapt)->FreeRcvBufferCount++; \
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ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) \
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>= (_pAdapt)->FreeRcvBufferCount); \
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ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
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(_Hdr)->State = SXG_BUFFER_FREE; \
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InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
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}
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#define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
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ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
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(_Hdr)->State = SXG_BUFFER_FREE; \
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(_pAdapt)->FreeRcvBlockCount++; \
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ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
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InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
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}
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/* SGL macros */
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#define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
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spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
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(_pAdapt)->FreeSglBufferCount++; \
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ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount); \
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ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
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(_Sgl)->State = SXG_BUFFER_FREE; \
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InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
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spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags); \
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}
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/*
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* Get an SGL buffer from the free queue. The first part of this macro
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* attempts to keep ahead of buffer depletion by allocating more when
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* we hit a minimum threshold. Note that we don't grab the lock
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* until after that. We're dealing with round numbers here, so we don't need to,
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* and not grabbing it avoids a possible double-trip.
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*/
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#define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl, _irq) { \
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struct list_entry *_ple; \
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if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
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|
||||||
(_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
|
|
||||||
(atomic_read(&_pAdapt->pending_allocations) == 0)) { \
|
|
||||||
sxg_allocate_buffer_memory(_pAdapt, \
|
|
||||||
(sizeof(struct sxg_scatter_gather) + SXG_SGL_BUF_SIZE),\
|
|
||||||
SXG_BUFFER_TYPE_SGL); \
|
|
||||||
} \
|
|
||||||
_Sgl = NULL; \
|
|
||||||
if(!_irq) \
|
|
||||||
spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
|
|
||||||
else \
|
|
||||||
spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
|
|
||||||
if((_pAdapt)->FreeSglBufferCount) { \
|
|
||||||
ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
|
|
||||||
_ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
|
|
||||||
(_Sgl) = container_of(_ple, struct sxg_scatter_gather, \
|
|
||||||
FreeList); \
|
|
||||||
(_pAdapt)->FreeSglBufferCount--; \
|
|
||||||
ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
|
|
||||||
(_Sgl)->State = SXG_BUFFER_BUSY; \
|
|
||||||
(_Sgl)->pSgl = NULL; \
|
|
||||||
} \
|
|
||||||
if(!_irq) \
|
|
||||||
spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);\
|
|
||||||
else \
|
|
||||||
spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);\
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* struct sxg_multicast_address
|
|
||||||
* Linked list of multicast addresses.
|
|
||||||
*/
|
|
||||||
struct sxg_multicast_address {
|
|
||||||
unsigned char Address[6];
|
|
||||||
struct sxg_multicast_address *Next;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Structure to maintain chimney send and receive buffer queues.
|
|
||||||
* This structure maintains NET_BUFFER_LIST queues that are
|
|
||||||
* given to us via the Chimney MiniportTcpOffloadSend and
|
|
||||||
* MiniportTcpOffloadReceive routines. This structure DOES NOT
|
|
||||||
* manage our data buffer queue
|
|
||||||
*/
|
|
||||||
struct sxg_buffer_queue {
|
|
||||||
u32 Type; /* Slow or fast - See below */
|
|
||||||
u32 Direction; /* Xmt or Rcv */
|
|
||||||
u32 Bytes; /* Byte count */
|
|
||||||
u32 * Head; /* Send queue head */
|
|
||||||
u32 * Tail; /* Send queue tail */
|
|
||||||
/* PNET_BUFFER_LIST NextNBL;*/ /* Short cut - next NBL */
|
|
||||||
/* PNET_BUFFER NextNB; */ /* Short cut - next NB */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define SXG_SLOW_SEND_BUFFER 0
|
|
||||||
#define SXG_FAST_SEND_BUFFER 1
|
|
||||||
#define SXG_RECEIVE_BUFFER 2
|
|
||||||
|
|
||||||
#define SXG_INIT_BUFFER(_Buffer, _Type) { \
|
|
||||||
(_Buffer)->Type = (_Type); \
|
|
||||||
if((_Type) == SXG_RECEIVE_BUFFER) { \
|
|
||||||
(_Buffer)->Direction = 0; \
|
|
||||||
} else { \
|
|
||||||
(_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
|
|
||||||
} \
|
|
||||||
(_Buffer)->Bytes = 0; \
|
|
||||||
(_Buffer)->Head = NULL; \
|
|
||||||
(_Buffer)->Tail = NULL; \
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
#define SXG_RSS_CPU_COUNT(_pAdapt) \
|
|
||||||
((_pAdapt)->RssEnabled ? NR_CPUS : 1)
|
|
||||||
|
|
||||||
/* DRIVER and ADAPTER structures */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Adapter states - These states closely match the adapter states
|
|
||||||
* documented in the DDK (with a few exceptions).
|
|
||||||
*/
|
|
||||||
enum SXG_STATE {
|
|
||||||
SXG_STATE_INITIALIZING, /* Initializing */
|
|
||||||
SXG_STATE_BOOTDIAG, /* Boot-Diagnostic mode */
|
|
||||||
SXG_STATE_PAUSING, /* Pausing */
|
|
||||||
SXG_STATE_PAUSED, /* Paused */
|
|
||||||
SXG_STATE_RUNNING, /* Running */
|
|
||||||
SXG_STATE_RESETTING, /* Reset in progress */
|
|
||||||
SXG_STATE_SLEEP, /* Sleeping */
|
|
||||||
SXG_STATE_DIAG, /* Diagnostic mode */
|
|
||||||
SXG_STATE_HALTING, /* Halting */
|
|
||||||
SXG_STATE_HALTED, /* Down or not-initialized */
|
|
||||||
SXG_STATE_SHUTDOWN /* shutdown */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Link state */
|
|
||||||
enum SXG_LINK_STATE {
|
|
||||||
SXG_LINK_DOWN,
|
|
||||||
SXG_LINK_UP
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Link initialization timeout in 100us units */
|
|
||||||
#define SXG_LINK_TIMEOUT 100000 /* 10 Seconds - REDUCE! */
|
|
||||||
|
|
||||||
|
|
||||||
/* Microcode file selection codes */
|
|
||||||
enum SXG_UCODE_SEL {
|
|
||||||
SXG_UCODE_SYSTEM, /* System (operational) uucode */
|
|
||||||
SXG_UCODE_SDIAGCPU, /* System CPU diagnostic ucode */
|
|
||||||
SXG_UCODE_SDIAGSYS /* System diagnostic ucode */
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
#define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
|
|
||||||
#define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
|
|
||||||
|
|
||||||
/* This probably lives in a proto.h file. Move later */
|
|
||||||
#define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
|
|
||||||
#define SXG_BROADCAST_PACKET(_pether) \
|
|
||||||
((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
|
|
||||||
(*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
|
|
||||||
|
|
||||||
/* For DbgPrints */
|
|
||||||
#define SXG_ID DPFLTR_IHVNETWORK_ID
|
|
||||||
#define SXG_ERROR DPFLTR_ERROR_LEVEL
|
|
||||||
|
|
||||||
/*
|
|
||||||
* struct sxg_driver structure -
|
|
||||||
*
|
|
||||||
* contains information about the sxg driver. There is only
|
|
||||||
* one of these, and it is defined as a global.
|
|
||||||
*/
|
|
||||||
|
|
||||||
struct sxg_driver {
|
|
||||||
struct adapter_t *Adapters; /* Linked list of adapters */
|
|
||||||
ushort AdapterID; /* Maintain unique adapter ID */
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef STATUS_SUCCESS
|
|
||||||
#undef STATUS_SUCCESS
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* TODO: We need to try and use NETDEV_TX_* before posting this out */
|
|
||||||
#define STATUS_SUCCESS 0
|
|
||||||
#define STATUS_PENDING 0
|
|
||||||
#define STATUS_FAILURE -1
|
|
||||||
#define STATUS_ERROR -2
|
|
||||||
#define STATUS_NOT_SUPPORTED -3
|
|
||||||
#define STATUS_BUFFER_TOO_SHORT -4
|
|
||||||
#define STATUS_RESOURCES -5
|
|
||||||
|
|
||||||
#define SLIC_MAX_CARDS 32
|
|
||||||
#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
|
|
||||||
#if SLIC_DUMP_ENABLED
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Dump buffer size
|
|
||||||
* This cannot be bigger than the max DMA size the card supports,
|
|
||||||
* given the current code structure in the host and ucode.
|
|
||||||
* Mojave supports 16K, Oasis supports 16K-1, so
|
|
||||||
* just set this at 15K, shouldnt make that much of a diff.
|
|
||||||
*/
|
|
||||||
#define DUMP_BUF_SIZE 0x3C00
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
|
|
||||||
#define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
|
|
||||||
|
|
||||||
struct mcast_address {
|
|
||||||
unsigned char address[6];
|
|
||||||
struct mcast_address *next;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define CARD_DOWN 0x00000000
|
|
||||||
#define CARD_UP 0x00000001
|
|
||||||
#define CARD_FAIL 0x00000002
|
|
||||||
#define CARD_DIAG 0x00000003
|
|
||||||
#define CARD_SLEEP 0x00000004
|
|
||||||
|
|
||||||
#define ADAPT_DOWN 0x00
|
|
||||||
#define ADAPT_UP 0x01
|
|
||||||
#define ADAPT_FAIL 0x02
|
|
||||||
#define ADAPT_RESET 0x03
|
|
||||||
#define ADAPT_SLEEP 0x04
|
|
||||||
|
|
||||||
#define ADAPT_FLAGS_BOOTTIME 0x0001
|
|
||||||
#define ADAPT_FLAGS_IS64BIT 0x0002
|
|
||||||
#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
|
|
||||||
#define ADAPT_FLAGS_FIBERMEDIA 0x0008
|
|
||||||
#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
|
|
||||||
#define ADAPT_FLAGS_INT_REGISTERED 0x0020
|
|
||||||
#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
|
|
||||||
#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
|
|
||||||
#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
|
|
||||||
|
|
||||||
#define LINK_DOWN 0x00
|
|
||||||
#define LINK_CONFIG 0x01
|
|
||||||
#define LINK_UP 0x02
|
|
||||||
|
|
||||||
#define LINK_10MB 0x00
|
|
||||||
#define LINK_100MB 0x01
|
|
||||||
#define LINK_AUTOSPEED 0x02
|
|
||||||
#define LINK_1000MB 0x03
|
|
||||||
#define LINK_10000MB 0x04
|
|
||||||
|
|
||||||
#define LINK_HALFD 0x00
|
|
||||||
#define LINK_FULLD 0x01
|
|
||||||
#define LINK_AUTOD 0x02
|
|
||||||
|
|
||||||
#define MAC_DIRECTED 0x00000001
|
|
||||||
#define MAC_BCAST 0x00000002
|
|
||||||
#define MAC_MCAST 0x00000004
|
|
||||||
#define MAC_PROMISC 0x00000008
|
|
||||||
#define MAC_LOOPBACK 0x00000010
|
|
||||||
#define MAC_ALLMCAST 0x00000020
|
|
||||||
|
|
||||||
#define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
|
|
||||||
#define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : \
|
|
||||||
((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
|
|
||||||
#define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
|
|
||||||
#define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
|
|
||||||
#define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
|
|
||||||
|
|
||||||
|
|
||||||
struct ether_header {
|
|
||||||
unsigned char ether_dhost[6];
|
|
||||||
unsigned char ether_shost[6];
|
|
||||||
ushort ether_type;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
#define NUM_CFG_SPACES 2
|
|
||||||
#define NUM_CFG_REGS 64
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We split LSS sends across four microcode queues derived from
|
|
||||||
* destination TCP port (if TCP/IP).
|
|
||||||
*/
|
|
||||||
#define SXG_LARGE_SEND_QUEUE_MASK 0x3
|
|
||||||
#define ISCSI_PORT 0xbc0c /* 3260 */
|
|
||||||
|
|
||||||
struct physcard {
|
|
||||||
struct adapter_t *adapter[SLIC_MAX_PORTS];
|
|
||||||
struct physcard *next;
|
|
||||||
unsigned int adapters_allocd;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct sxgbase_driver {
|
|
||||||
spinlock_t driver_lock;
|
|
||||||
unsigned long flags; /* irqsave for spinlock */
|
|
||||||
u32 num_sxg_cards;
|
|
||||||
u32 num_sxg_ports;
|
|
||||||
u32 num_sxg_ports_active;
|
|
||||||
u32 dynamic_intagg;
|
|
||||||
struct physcard *phys_card;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
struct adapter_t {
|
|
||||||
void * ifp;
|
|
||||||
unsigned int port;
|
|
||||||
struct napi_struct napi;
|
|
||||||
struct physcard *physcard;
|
|
||||||
unsigned int physport;
|
|
||||||
unsigned int slotnumber;
|
|
||||||
unsigned int functionnumber;
|
|
||||||
ushort vendid;
|
|
||||||
ushort devid;
|
|
||||||
ushort subsysid;
|
|
||||||
u32 irq;
|
|
||||||
|
|
||||||
void __iomem * base_addr;
|
|
||||||
u32 memorylength;
|
|
||||||
u32 drambase;
|
|
||||||
u32 dramlength;
|
|
||||||
enum asic_type asictype; /* type of ASIC (chip) */
|
|
||||||
unsigned int activated;
|
|
||||||
u32 intrregistered;
|
|
||||||
unsigned int isp_initialized;
|
|
||||||
unsigned char state;
|
|
||||||
unsigned char linkstate;
|
|
||||||
unsigned int flags;
|
|
||||||
unsigned char macaddr[6];
|
|
||||||
unsigned char currmacaddr[6];
|
|
||||||
u32 macopts;
|
|
||||||
ushort devflags_prev;
|
|
||||||
u64 mcastmask;
|
|
||||||
struct mcast_address *mcastaddrs;
|
|
||||||
struct timer_list pingtimer;
|
|
||||||
u32 pingtimerset;
|
|
||||||
struct timer_list statstimer;
|
|
||||||
u32 statstimerset;
|
|
||||||
struct timer_list vpci_timer;
|
|
||||||
u32 vpci_timerset;
|
|
||||||
struct timer_list loadtimer;
|
|
||||||
u32 loadtimerset;
|
|
||||||
|
|
||||||
u32 xmitq_full;
|
|
||||||
u32 all_reg_writes;
|
|
||||||
u32 icr_reg_writes;
|
|
||||||
u32 isr_reg_writes;
|
|
||||||
u32 error_interrupts;
|
|
||||||
u32 error_rmiss_interrupts;
|
|
||||||
u32 rx_errors;
|
|
||||||
u32 rcv_drops;
|
|
||||||
u32 rcv_interrupts;
|
|
||||||
u32 xmit_interrupts;
|
|
||||||
u32 linkevent_interrupts;
|
|
||||||
u32 upr_interrupts;
|
|
||||||
u32 num_isrs;
|
|
||||||
u32 false_interrupts;
|
|
||||||
u32 tx_packets;
|
|
||||||
u32 xmit_completes;
|
|
||||||
u32 tx_drops;
|
|
||||||
u32 rcv_broadcasts;
|
|
||||||
u32 rcv_multicasts;
|
|
||||||
u32 rcv_unicasts;
|
|
||||||
u32 max_isr_rcvs;
|
|
||||||
u32 max_isr_xmits;
|
|
||||||
u32 rcv_interrupt_yields;
|
|
||||||
u32 intagg_period;
|
|
||||||
struct net_device_stats stats;
|
|
||||||
u32 * MiniportHandle; /* Our miniport handle */
|
|
||||||
enum SXG_STATE State; /* Adapter state */
|
|
||||||
enum SXG_LINK_STATE LinkState; /* Link state */
|
|
||||||
u64 LinkSpeed; /* Link Speed */
|
|
||||||
u32 PowerState; /* NDIS power state */
|
|
||||||
struct adapter_t *Next; /* Linked list */
|
|
||||||
ushort AdapterID; /* 1..n */
|
|
||||||
struct net_device * netdev;
|
|
||||||
struct net_device * next_netdevice;
|
|
||||||
struct pci_dev *pcidev;
|
|
||||||
|
|
||||||
struct sxg_multicast_address *MulticastAddrs; /* Multicast list */
|
|
||||||
u64 MulticastMask; /* Multicast mask */
|
|
||||||
u32 *InterruptHandle; /* Register Interrupt handle */
|
|
||||||
u32 InterruptLevel; /* From Resource list */
|
|
||||||
u32 InterruptVector; /* From Resource list */
|
|
||||||
spinlock_t AdapterLock; /* Serialize access adapter routines */
|
|
||||||
spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
|
|
||||||
struct sxg_hw_regs *HwRegs; /* Sahara HW Register Memory (BAR0/1) */
|
|
||||||
struct sxg_ucode_regs *UcodeRegs; /* Microcode Register Memory (BAR2/3) */
|
|
||||||
struct sxg_tcb_regs *TcbRegs; /* Same as Ucode regs - See sxghw.h */
|
|
||||||
ushort FrameSize; /* Maximum frame size */
|
|
||||||
u32 * DmaHandle; /* NDIS DMA handle */
|
|
||||||
u32 * PacketPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
|
|
||||||
u32 * BufferPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
|
|
||||||
u32 MacFilter; /* NDIS MAC Filter */
|
|
||||||
struct sxg_event_ring *EventRings; /* Host event rings. 1/CPU to 16 max */
|
|
||||||
dma_addr_t PEventRings; /* Physical address */
|
|
||||||
u32 NextEvent[SXG_MAX_RSS]; /* Current location in ring */
|
|
||||||
dma_addr_t PTcbBuffers; /* TCB Buffers - physical address */
|
|
||||||
dma_addr_t PTcbCompBuffers; /* TCB Composite Buffers - phys addr */
|
|
||||||
struct sxg_xmt_ring *XmtRings; /* Transmit rings */
|
|
||||||
dma_addr_t PXmtRings; /* Transmit rings - physical address */
|
|
||||||
struct sxg_ring_info XmtRingZeroInfo; /* Transmit ring 0 info */
|
|
||||||
|
|
||||||
spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
|
|
||||||
u32 * XmtRingZeroIndex; /* Shared XMT ring 0 index */
|
|
||||||
dma_addr_t PXmtRingZeroIndex; /* Shared XMT ring 0 index - physical */
|
|
||||||
struct list_entry FreeProtocolHeaders;/* Free protocol headers */
|
|
||||||
u32 FreeProtoHdrCount; /* Count */
|
|
||||||
void * ProtocolHeaders; /* Block of protocol header */
|
|
||||||
dma_addr_t PProtocolHeaders; /* Block of protocol headers - phys */
|
|
||||||
|
|
||||||
struct sxg_rcv_ring *RcvRings; /* Receive rings */
|
|
||||||
dma_addr_t PRcvRings; /* Receive rings - physical address */
|
|
||||||
struct sxg_ucode_stats *ucode_stats; /* Ucode Stats */
|
|
||||||
/* Ucode Stats - physical address */
|
|
||||||
dma_addr_t pucode_stats;
|
|
||||||
|
|
||||||
struct sxg_ring_info RcvRingZeroInfo; /* Receive ring 0 info */
|
|
||||||
|
|
||||||
u32 * Isr; /* Interrupt status register */
|
|
||||||
dma_addr_t PIsr; /* ISR - physical address */
|
|
||||||
u32 IsrCopy[SXG_MAX_RSS]; /* Copy of ISR */
|
|
||||||
ushort InterruptsEnabled; /* Bitmask of enabled vectors */
|
|
||||||
unsigned char *IndirectionTable; /* RSS indirection table */
|
|
||||||
dma_addr_t PIndirectionTable; /* Physical address */
|
|
||||||
ushort RssTableSize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
|
|
||||||
ushort HashKeySize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
|
|
||||||
unsigned char HashSecretKey[40]; /* rss key */
|
|
||||||
u32 HashInformation;
|
|
||||||
/* Receive buffer queues */
|
|
||||||
spinlock_t RcvQLock; /* Receive Queue Lock */
|
|
||||||
struct list_entry FreeRcvBuffers; /* Free SXG_DATA_BUFFER queue */
|
|
||||||
struct list_entry FreeRcvBlocks; /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
|
|
||||||
struct list_entry AllRcvBlocks; /* All SXG_RCV_BLOCKs */
|
|
||||||
ushort FreeRcvBufferCount; /* Number of free rcv data buffers */
|
|
||||||
ushort FreeRcvBlockCount; /* # of free rcv descriptor blocks */
|
|
||||||
ushort AllRcvBlockCount; /* Number of total receive blocks */
|
|
||||||
ushort ReceiveBufferSize; /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
|
|
||||||
/* Converted this to a atomic variable
|
|
||||||
u32 AllocationsPending; */
|
|
||||||
atomic_t pending_allocations;
|
|
||||||
u32 AllocationsPending; /* Receive allocation pending */
|
|
||||||
u32 RcvBuffersOnCard; /* SXG_DATA_BUFFERS owned by card */
|
|
||||||
/* SGL buffers */
|
|
||||||
spinlock_t SglQLock; /* SGL Queue Lock */
|
|
||||||
struct list_entry FreeSglBuffers; /* Free struct sxg_scatter_gather */
|
|
||||||
struct list_entry AllSglBuffers; /* All struct sxg_scatter_gather */
|
|
||||||
ushort FreeSglBufferCount; /* Number of free SGL buffers */
|
|
||||||
ushort AllSglBufferCount; /* Number of total SGL buffers */
|
|
||||||
u32 CurrentTime; /* Tick count */
|
|
||||||
u32 FastpathConnections;/* # of fastpath connections */
|
|
||||||
/* Various single-bit flags: */
|
|
||||||
u32 BasicAllocations:1; /* Locks and listheads */
|
|
||||||
u32 IntRegistered:1; /* Interrupt registered */
|
|
||||||
u32 PingOutstanding:1; /* Ping outstanding to card */
|
|
||||||
u32 Dead:1; /* Card dead */
|
|
||||||
u32 DumpDriver:1; /* OID_SLIC_DRIVER_DUMP request */
|
|
||||||
u32 DumpCard:1; /* OID_SLIC_CARD_DUMP request */
|
|
||||||
u32 DumpCmdRunning:1; /* Dump command in progress */
|
|
||||||
u32 DebugRunning:1; /* AGDB debug in progress */
|
|
||||||
u32 JumboEnabled:1; /* Jumbo frames enabled */
|
|
||||||
u32 msi_enabled:1; /* MSI interrupt enabled */
|
|
||||||
u32 RssEnabled:1; /* RSS Enabled */
|
|
||||||
u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
|
|
||||||
u32 DiagStart:1; /* Init adapter for diagnostic start */
|
|
||||||
u32 XmtFcEnabled:1;
|
|
||||||
u32 RcvFcEnabled:1;
|
|
||||||
/* Stats */
|
|
||||||
u32 PendingRcvCount; /* Outstanding rcv indications */
|
|
||||||
u32 PendingXmtCount; /* Outstanding send requests */
|
|
||||||
struct sxg_stats Stats; /* Statistics */
|
|
||||||
u32 ReassBufs; /* Number of reassembly buffers */
|
|
||||||
/* Card Crash Info */
|
|
||||||
ushort CrashLocation; /* Microcode crash location */
|
|
||||||
unsigned char CrashCpu; /* Sahara CPU ID */
|
|
||||||
/* Diagnostics */
|
|
||||||
/* PDIAG_CMD DiagCmds; */ /* List of free diagnostic commands */
|
|
||||||
/* PDIAG_BUFFER DiagBuffers; */ /* List of free diagnostic buffers */
|
|
||||||
/* PDIAG_REQ DiagReqQ; */ /* List of outstanding (asynchronous) diag requests */
|
|
||||||
/* u32 DiagCmdTimeout; */ /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
|
|
||||||
/* unsigned char DiagDmaDesc[DMA_CPU_CTXS]; */ /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
|
|
||||||
/*
|
|
||||||
* Put preprocessor-conditional fields at the end so we don't
|
|
||||||
* have to recompile sxgdbg everytime we reconfigure the driver
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_X86)
|
|
||||||
u32 AddrUpper; /* Upper 32 bits of 64-bit register */
|
|
||||||
#endif
|
|
||||||
unsigned short max_aggregation;
|
|
||||||
unsigned short min_aggregation;
|
|
||||||
/*#if SXG_FAILURE_DUMP */
|
|
||||||
/* NDIS_EVENT DumpThreadEvent; */ /* syncronize dump thread */
|
|
||||||
/* BOOLEAN DumpThreadRunning; */ /* termination flag */
|
|
||||||
/* PSXG_DUMP_CMD DumpBuffer; */ /* 68k - Cmd and Buffer */
|
|
||||||
/* dma_addr_t PDumpBuffer; */ /* Physical address */
|
|
||||||
/*#endif */ /* SXG_FAILURE_DUMP */
|
|
||||||
/*MSI-X related data elements*/
|
|
||||||
u32 nr_msix_entries;
|
|
||||||
struct msix_entry *msi_entries;
|
|
||||||
struct timer_list watchdog_timer;
|
|
||||||
struct work_struct update_link_status;
|
|
||||||
u32 link_status_changed;
|
|
||||||
};
|
|
||||||
|
|
||||||
#if SLIC_DUMP_ENABLED
|
|
||||||
#define SLIC_DUMP_REQUESTED 1
|
|
||||||
#define SLIC_DUMP_IN_PROGRESS 2
|
|
||||||
#define SLIC_DUMP_DONE 3
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Microcode crash information structure. This
|
|
||||||
* structure is written out to the card's SRAM when the microcode panic's.
|
|
||||||
*/
|
|
||||||
struct slic_crash_info {
|
|
||||||
ushort cpu_id;
|
|
||||||
ushort crash_pc;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define CRASH_INFO_OFFSET 0x155C
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define UPDATE_STATS(largestat, newstat, oldstat) \
|
|
||||||
{ \
|
|
||||||
if ((newstat) < (oldstat)) \
|
|
||||||
(largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
|
|
||||||
else \
|
|
||||||
(largestat) += ((newstat) - (oldstat)); \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define UPDATE_STATS_GB(largestat, newstat, oldstat) \
|
|
||||||
{ \
|
|
||||||
(largestat) += ((newstat) - (oldstat)); \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
|
|
||||||
{ \
|
|
||||||
_Result = TRUE; \
|
|
||||||
if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
|
|
||||||
_Result = FALSE; \
|
|
||||||
if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
|
|
||||||
_Result = FALSE; \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define ETHERMAXFRAME 1514
|
|
||||||
#define JUMBOMAXFRAME 9014
|
|
||||||
|
|
||||||
#define SXG_JUMBO_MTU 9000
|
|
||||||
#define SXG_DEFAULT_MTU 1500
|
|
||||||
|
|
||||||
#if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
|
|
||||||
#define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
|
|
||||||
#define SXG_GET_ADDR_HIGH(_addr) \
|
|
||||||
(u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
|
|
||||||
#else
|
|
||||||
#define SXG_GET_ADDR_LOW(_addr) (u32)_addr
|
|
||||||
#define SXG_GET_ADDR_HIGH(_addr) (u32)0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define FLUSH TRUE
|
|
||||||
#define DONT_FLUSH FALSE
|
|
||||||
|
|
||||||
#define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
|
|
||||||
#define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
|
|
||||||
#define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
|
|
||||||
|
|
||||||
extern const struct ethtool_ops sxg_nic_ethtool_ops;
|
|
||||||
#define SXG_COMPLETE_SLOW_SEND_LIMIT 128
|
|
||||||
#endif /* __SXG_DRIVER_H__ */
|
|
||||||
@ -1,328 +0,0 @@
|
|||||||
/**************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above
|
|
||||||
* copyright notice, this list of conditions and the following
|
|
||||||
* disclaimer in the documentation and/or other materials provided
|
|
||||||
* with the distribution.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
|
|
||||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
|
||||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
||||||
* SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* The views and conclusions contained in the software and documentation
|
|
||||||
* are those of the authors and should not be interpreted as representing
|
|
||||||
* official policies, either expressed or implied, of Alacritech, Inc.
|
|
||||||
*
|
|
||||||
**************************************************************************/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FILENAME: sxg_ethtool.c
|
|
||||||
*
|
|
||||||
* The ethtool support for SXG driver for Alacritech's 10Gbe products.
|
|
||||||
*
|
|
||||||
* NOTE: This is the standard, non-accelerated version of Alacritech's
|
|
||||||
* IS-NIC driver.
|
|
||||||
*/
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/errno.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/netdevice.h>
|
|
||||||
#include <linux/etherdevice.h>
|
|
||||||
#include <linux/ethtool.h>
|
|
||||||
#include <linux/skbuff.h>
|
|
||||||
#include <linux/pci.h>
|
|
||||||
|
|
||||||
#include "sxg_os.h"
|
|
||||||
#include "sxghw.h"
|
|
||||||
#include "sxghif.h"
|
|
||||||
#include "sxg.h"
|
|
||||||
|
|
||||||
struct sxg_nic_stats {
|
|
||||||
char stat_string[ETH_GSTRING_LEN];
|
|
||||||
int sizeof_stat;
|
|
||||||
int stat_offset;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define SXG_NIC_STATS(m) sizeof(((struct adapter_t *)0)->m), \
|
|
||||||
offsetof(struct adapter_t, m)
|
|
||||||
|
|
||||||
#define USER_VIEWABLE_EEPROM_SIZE 28
|
|
||||||
|
|
||||||
static struct sxg_nic_stats sxg_nic_gstrings_stats[] = {
|
|
||||||
{"xmit_ring_0_full", SXG_NIC_STATS(Stats.XmtZeroFull)},
|
|
||||||
|
|
||||||
/* May be will need in future */
|
|
||||||
/* {"dumb_xmit_broadcast_packets", SXG_NIC_STATS(Stats.DumbXmtBcastPkts)},
|
|
||||||
{"dumb_xmit_broadcast_bytes", SXG_NIC_STATS(Stats.DumbXmtBcastBytes)},
|
|
||||||
{"dumb_xmit_unicast_packets", SXG_NIC_STATS(Stats.DumbXmtUcastPkts)},
|
|
||||||
{"dumb_xmit_unicast_bytes", SXG_NIC_STATS(Stats.DumbXmtUcastBytes)},
|
|
||||||
*/
|
|
||||||
{"xmit_queue_length", SXG_NIC_STATS(Stats.XmtQLen)},
|
|
||||||
{"memory_allocation_failure", SXG_NIC_STATS(Stats.NoMem)},
|
|
||||||
{"Interrupts", SXG_NIC_STATS(Stats.NumInts)},
|
|
||||||
{"false_interrupts", SXG_NIC_STATS(Stats.FalseInts)},
|
|
||||||
{"processed_data_queue_full", SXG_NIC_STATS(Stats.PdqFull)},
|
|
||||||
{"event_ring_full", SXG_NIC_STATS(Stats.EventRingFull)},
|
|
||||||
{"transport_checksum_error", SXG_NIC_STATS(Stats.TransportCsum)},
|
|
||||||
{"transport_underflow_error", SXG_NIC_STATS(Stats.TransportUflow)},
|
|
||||||
{"transport_header_length_error", SXG_NIC_STATS(Stats.TransportHdrLen)},
|
|
||||||
{"network_checksum_error", SXG_NIC_STATS(Stats.NetworkCsum)},
|
|
||||||
{"network_underflow_error", SXG_NIC_STATS(Stats.NetworkUflow)},
|
|
||||||
{"network_header_length_error", SXG_NIC_STATS(Stats.NetworkHdrLen)},
|
|
||||||
{"receive_parity_error", SXG_NIC_STATS(Stats.Parity)},
|
|
||||||
{"link_parity_error", SXG_NIC_STATS(Stats.LinkParity)},
|
|
||||||
{"link/data early_error", SXG_NIC_STATS(Stats.LinkEarly)},
|
|
||||||
{"buffer_overflow_error", SXG_NIC_STATS(Stats.LinkBufOflow)},
|
|
||||||
{"link_code_error", SXG_NIC_STATS(Stats.LinkCode)},
|
|
||||||
{"dribble nibble", SXG_NIC_STATS(Stats.LinkDribble)},
|
|
||||||
{"CRC_error", SXG_NIC_STATS(Stats.LinkCrc)},
|
|
||||||
{"link_overflow_error", SXG_NIC_STATS(Stats.LinkOflow)},
|
|
||||||
{"link_underflow_error", SXG_NIC_STATS(Stats.LinkUflow)},
|
|
||||||
|
|
||||||
/* May be need in future */
|
|
||||||
/* {"dumb_rcv_broadcast_packets", SXG_NIC_STATS(Stats.DumbRcvBcastPkts)},
|
|
||||||
{"dumb_rcv_broadcast_bytes", SXG_NIC_STATS(Stats.DumbRcvBcastBytes)},
|
|
||||||
*/ {"dumb_rcv_multicast_packets", SXG_NIC_STATS(Stats.DumbRcvMcastPkts)},
|
|
||||||
{"dumb_rcv_multicast_bytes", SXG_NIC_STATS(Stats.DumbRcvMcastBytes)},
|
|
||||||
/* {"dumb_rcv_unicast_packets", SXG_NIC_STATS(Stats.DumbRcvUcastPkts)},
|
|
||||||
{"dumb_rcv_unicast_bytes", SXG_NIC_STATS(Stats.DumbRcvUcastBytes)},
|
|
||||||
*/
|
|
||||||
{"no_sgl_buffer", SXG_NIC_STATS(Stats.NoSglBuf)},
|
|
||||||
};
|
|
||||||
|
|
||||||
#define SXG_NIC_STATS_LEN ARRAY_SIZE(sxg_nic_gstrings_stats)
|
|
||||||
|
|
||||||
static inline void sxg_reg32_write(void __iomem *reg, u32 value, bool flush)
|
|
||||||
{
|
|
||||||
writel(value, reg);
|
|
||||||
if (flush)
|
|
||||||
mb();
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void sxg_reg64_write(struct adapter_t *adapter, void __iomem *reg,
|
|
||||||
u64 value, u32 cpu)
|
|
||||||
{
|
|
||||||
u32 value_high = (u32) (value >> 32);
|
|
||||||
u32 value_low = (u32) (value & 0x00000000FFFFFFFF);
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&adapter->Bit64RegLock, flags);
|
|
||||||
writel(value_high, (void __iomem *)(&adapter->UcodeRegs[cpu].Upper));
|
|
||||||
writel(value_low, reg);
|
|
||||||
spin_unlock_irqrestore(&adapter->Bit64RegLock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
sxg_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(dev);
|
|
||||||
strncpy(drvinfo->driver, sxg_driver_name, 32);
|
|
||||||
strncpy(drvinfo->version, SXG_DRV_VERSION, 32);
|
|
||||||
// strncpy(drvinfo->fw_version, SAHARA_UCODE_VERS_STRING, 32);
|
|
||||||
strncpy(drvinfo->bus_info, pci_name(adapter->pcidev), 32);
|
|
||||||
/* TODO : Read the major and minor number of firmware. Is this
|
|
||||||
* from the FLASH/EEPROM or download file ?
|
|
||||||
*/
|
|
||||||
/* LINSYS : Check if this is correct or if not find the right value
|
|
||||||
* Also check what is the right EEPROM length : EEPROM_SIZE_XFMR or EEPROM_SIZE_NO_XFMR
|
|
||||||
*/
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_set_settings(struct net_device *netdev,
|
|
||||||
struct ethtool_cmd *ecmd)
|
|
||||||
{
|
|
||||||
/* No settings are applicable as we support only 10Gb/FIBRE_media */
|
|
||||||
return -EOPNOTSUPP;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
sxg_nic_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
|
|
||||||
{
|
|
||||||
int index;
|
|
||||||
|
|
||||||
switch(stringset) {
|
|
||||||
case ETH_SS_TEST:
|
|
||||||
break;
|
|
||||||
case ETH_SS_STATS:
|
|
||||||
for (index = 0; index < SXG_NIC_STATS_LEN; index++) {
|
|
||||||
memcpy(data + index * ETH_GSTRING_LEN,
|
|
||||||
sxg_nic_gstrings_stats[index].stat_string,
|
|
||||||
ETH_GSTRING_LEN);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
sxg_nic_get_ethtool_stats(struct net_device *netdev,
|
|
||||||
struct ethtool_stats *stats, u64 * data)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(netdev);
|
|
||||||
int index;
|
|
||||||
for (index = 0; index < SXG_NIC_STATS_LEN; index++) {
|
|
||||||
char *p = (char *)adapter +
|
|
||||||
sxg_nic_gstrings_stats[index].stat_offset;
|
|
||||||
data[index] = (sxg_nic_gstrings_stats[index].sizeof_stat ==
|
|
||||||
sizeof(u64)) ? *(u64 *) p : *(u32 *) p;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_get_sset_count(struct net_device *netdev, int sset)
|
|
||||||
{
|
|
||||||
switch (sset) {
|
|
||||||
case ETH_SS_STATS:
|
|
||||||
return SXG_NIC_STATS_LEN;
|
|
||||||
default:
|
|
||||||
return -EOPNOTSUPP;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_get_settings(struct net_device *netdev,
|
|
||||||
struct ethtool_cmd *ecmd)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(netdev);
|
|
||||||
|
|
||||||
ecmd->supported = SUPPORTED_10000baseT_Full;
|
|
||||||
ecmd->autoneg = AUTONEG_ENABLE; //VSS check This
|
|
||||||
ecmd->transceiver = XCVR_EXTERNAL; //VSS check This
|
|
||||||
|
|
||||||
/* For Fibre Channel */
|
|
||||||
ecmd->supported |= SUPPORTED_FIBRE;
|
|
||||||
ecmd->advertising = (ADVERTISED_10000baseT_Full |
|
|
||||||
ADVERTISED_FIBRE);
|
|
||||||
ecmd->port = PORT_FIBRE;
|
|
||||||
|
|
||||||
|
|
||||||
/* Link Speed */
|
|
||||||
if(adapter->LinkState & SXG_LINK_UP) {
|
|
||||||
ecmd->speed = SPEED_10000; //adapter->LinkSpeed;
|
|
||||||
ecmd->duplex = DUPLEX_FULL;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static u32 sxg_nic_get_rx_csum(struct net_device *netdev)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(netdev);
|
|
||||||
return ((adapter->flags & SXG_RCV_IP_CSUM_ENABLED) &&
|
|
||||||
(adapter->flags & SXG_RCV_TCP_CSUM_ENABLED));
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_set_rx_csum(struct net_device *netdev, u32 data)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(netdev);
|
|
||||||
if (data)
|
|
||||||
adapter->flags |= SXG_RCV_IP_CSUM_ENABLED;
|
|
||||||
else
|
|
||||||
adapter->flags &= ~SXG_RCV_IP_CSUM_ENABLED;
|
|
||||||
/*
|
|
||||||
* We dont need to write to the card to do checksums.
|
|
||||||
* It does it anyways.
|
|
||||||
*/
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_get_regs_len(struct net_device *dev)
|
|
||||||
{
|
|
||||||
return (SXG_HWREG_MEMSIZE + SXG_UCODEREG_MEMSIZE);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void sxg_nic_get_regs(struct net_device *netdev,
|
|
||||||
struct ethtool_regs *regs, void *p)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(netdev);
|
|
||||||
struct sxg_hw_regs *HwRegs = adapter->HwRegs;
|
|
||||||
struct sxg_ucode_regs *UcodeRegs = adapter->UcodeRegs;
|
|
||||||
u32 *buff = p;
|
|
||||||
|
|
||||||
memset(p, 0, (sizeof(struct sxg_hw_regs)+sizeof(struct sxg_ucode_regs)));
|
|
||||||
memcpy(buff, HwRegs, sizeof(struct sxg_hw_regs));
|
|
||||||
memcpy((buff+sizeof(struct sxg_hw_regs)), UcodeRegs, sizeof(struct sxg_ucode_regs));
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_get_eeprom_len(struct net_device *netdev)
|
|
||||||
{
|
|
||||||
return (USER_VIEWABLE_EEPROM_SIZE);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sxg_nic_get_eeprom(struct net_device *netdev,
|
|
||||||
struct ethtool_eeprom *eeprom, u8 *bytes)
|
|
||||||
{
|
|
||||||
struct adapter_t *adapter = netdev_priv(netdev);
|
|
||||||
struct sw_cfg_data *data;
|
|
||||||
unsigned long i, status;
|
|
||||||
dma_addr_t p_addr;
|
|
||||||
|
|
||||||
data = pci_alloc_consistent(adapter->pcidev, sizeof(struct sw_cfg_data),
|
|
||||||
&p_addr);
|
|
||||||
if(!data) {
|
|
||||||
/*
|
|
||||||
* We cant get even this much memory. Raise a hell
|
|
||||||
* Get out of here
|
|
||||||
*/
|
|
||||||
printk(KERN_ERR"%s : Could not allocate memory for reading \
|
|
||||||
EEPROM\n", __func__);
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
|
|
||||||
WRITE_REG(adapter->UcodeRegs[0].ConfigStat, SXG_CFG_TIMEOUT, TRUE);
|
|
||||||
WRITE_REG64(adapter, adapter->UcodeRegs[0].Config, p_addr, 0);
|
|
||||||
for(i=0; i<1000; i++) {
|
|
||||||
READ_REG(adapter->UcodeRegs[0].ConfigStat, status);
|
|
||||||
if (status != SXG_CFG_TIMEOUT)
|
|
||||||
break;
|
|
||||||
mdelay(1); /* Do we really need this */
|
|
||||||
}
|
|
||||||
|
|
||||||
memset(bytes, 0, eeprom->len);
|
|
||||||
memcpy(bytes, data->MacAddr[0].MacAddr, sizeof(struct sxg_config_mac));
|
|
||||||
memcpy(bytes+6, data->AtkFru.PartNum, 6);
|
|
||||||
memcpy(bytes+12, data->AtkFru.Revision, 2);
|
|
||||||
memcpy(bytes+14, data->AtkFru.Serial, 14);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct ethtool_ops sxg_nic_ethtool_ops = {
|
|
||||||
.get_settings = sxg_nic_get_settings,
|
|
||||||
.set_settings = sxg_nic_set_settings,
|
|
||||||
.get_drvinfo = sxg_nic_get_drvinfo,
|
|
||||||
.get_regs_len = sxg_nic_get_regs_len,
|
|
||||||
.get_regs = sxg_nic_get_regs,
|
|
||||||
.get_link = ethtool_op_get_link,
|
|
||||||
// .get_wol = sxg_nic_get_wol,
|
|
||||||
.get_eeprom_len = sxg_nic_get_eeprom_len,
|
|
||||||
.get_eeprom = sxg_nic_get_eeprom,
|
|
||||||
// .get_pauseparam = sxg_nic_get_pauseparam,
|
|
||||||
// .set_pauseparam = sxg_nic_set_pauseparam,
|
|
||||||
.set_tx_csum = ethtool_op_set_tx_csum,
|
|
||||||
.get_sg = ethtool_op_get_sg,
|
|
||||||
.set_sg = ethtool_op_set_sg,
|
|
||||||
// .get_tso = sxg_nic_get_tso,
|
|
||||||
// .set_tso = sxg_nic_set_tso,
|
|
||||||
// .self_test = sxg_nic_diag_test,
|
|
||||||
.get_strings = sxg_nic_get_strings,
|
|
||||||
.get_ethtool_stats = sxg_nic_get_ethtool_stats,
|
|
||||||
.get_sset_count = sxg_nic_get_sset_count,
|
|
||||||
.get_rx_csum = sxg_nic_get_rx_csum,
|
|
||||||
.set_rx_csum = sxg_nic_set_rx_csum,
|
|
||||||
// .get_coalesce = sxg_nic_get_intr_coalesce,
|
|
||||||
// .set_coalesce = sxg_nic_set_intr_coalesce,
|
|
||||||
};
|
|
||||||
@ -1,149 +0,0 @@
|
|||||||
/**************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above
|
|
||||||
* copyright notice, this list of conditions and the following
|
|
||||||
* disclaimer in the documentation and/or other materials provided
|
|
||||||
* with the distribution.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
|
|
||||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
|
||||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
||||||
* SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* The views and conclusions contained in the software and documentation
|
|
||||||
* are those of the authors and should not be interpreted as representing
|
|
||||||
* official policies, either expressed or implied, of Alacritech, Inc.
|
|
||||||
*
|
|
||||||
**************************************************************************/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FILENAME: sxg_os.h
|
|
||||||
*
|
|
||||||
* These are the Linux-specific definitions required for the SLICOSS
|
|
||||||
* driver, which should allow for greater portability to other OSes.
|
|
||||||
*/
|
|
||||||
#ifndef _SLIC_OS_SPECIFIC_H_
|
|
||||||
#define _SLIC_OS_SPECIFIC_H_
|
|
||||||
|
|
||||||
#define FALSE (0)
|
|
||||||
#define TRUE (1)
|
|
||||||
|
|
||||||
struct list_entry {
|
|
||||||
struct list_entry *nle_flink;
|
|
||||||
struct list_entry *nle_blink;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define InitializeListHead(l) \
|
|
||||||
(l)->nle_flink = (l)->nle_blink = (l)
|
|
||||||
|
|
||||||
#define IsListEmpty(h) \
|
|
||||||
((h)->nle_flink == (h))
|
|
||||||
|
|
||||||
#define RemoveEntryList(e) \
|
|
||||||
do { \
|
|
||||||
list_entry *b; \
|
|
||||||
list_entry *f; \
|
|
||||||
\
|
|
||||||
f = (e)->nle_flink; \
|
|
||||||
b = (e)->nle_blink; \
|
|
||||||
b->nle_flink = f; \
|
|
||||||
f->nle_blink = b; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/* These two have to be inlined since they return things. */
|
|
||||||
|
|
||||||
static inline struct list_entry *RemoveHeadList(struct list_entry *l)
|
|
||||||
{
|
|
||||||
struct list_entry *f;
|
|
||||||
struct list_entry *e;
|
|
||||||
|
|
||||||
e = l->nle_flink;
|
|
||||||
f = e->nle_flink;
|
|
||||||
l->nle_flink = f;
|
|
||||||
f->nle_blink = l;
|
|
||||||
|
|
||||||
return (e);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline struct list_entry *RemoveTailList(struct list_entry *l)
|
|
||||||
{
|
|
||||||
struct list_entry *b;
|
|
||||||
struct list_entry *e;
|
|
||||||
|
|
||||||
e = l->nle_blink;
|
|
||||||
b = e->nle_blink;
|
|
||||||
l->nle_blink = b;
|
|
||||||
b->nle_flink = l;
|
|
||||||
|
|
||||||
return (e);
|
|
||||||
}
|
|
||||||
|
|
||||||
#define InsertTailList(l, e) \
|
|
||||||
do { \
|
|
||||||
struct list_entry *b; \
|
|
||||||
\
|
|
||||||
b = (l)->nle_blink; \
|
|
||||||
(e)->nle_flink = (l); \
|
|
||||||
(e)->nle_blink = b; \
|
|
||||||
b->nle_flink = (e); \
|
|
||||||
(l)->nle_blink = (e); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define InsertHeadList(l, e) \
|
|
||||||
do { \
|
|
||||||
struct list_entry *f; \
|
|
||||||
\
|
|
||||||
f = (l)->nle_flink; \
|
|
||||||
(e)->nle_flink = f; \
|
|
||||||
(e)->nle_blink = l; \
|
|
||||||
f->nle_blink = (e); \
|
|
||||||
(l)->nle_flink = (e); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define ATK_DEBUG 1
|
|
||||||
|
|
||||||
#if ATK_DEBUG
|
|
||||||
#define SLIC_TIMESTAMP(value) { \
|
|
||||||
struct timeval timev; \
|
|
||||||
do_gettimeofday(&timev); \
|
|
||||||
value = timev.tv_sec*1000000 + timev.tv_usec; \
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define SLIC_TIMESTAMP(value)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* SXG DEFINES */
|
|
||||||
|
|
||||||
#ifdef ATKDBG
|
|
||||||
#define SXG_TIMESTAMP(value) { \
|
|
||||||
struct timeval timev; \
|
|
||||||
do_gettimeofday(&timev); \
|
|
||||||
value = timev.tv_sec*1000000 + timev.tv_usec; \
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define SXG_TIMESTAMP(value)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define WRITE_REG(reg,value,flush) \
|
|
||||||
sxg_reg32_write((®), (value), (flush))
|
|
||||||
#define WRITE_REG64(a,reg,value,cpu) \
|
|
||||||
sxg_reg64_write((a),(®),(value),(cpu))
|
|
||||||
#define READ_REG(reg,value) (value) = readl((void __iomem *)(®))
|
|
||||||
|
|
||||||
#endif /* _SLIC_OS_SPECIFIC_H_ */
|
|
||||||
@ -1,184 +0,0 @@
|
|||||||
/**************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Id: sxgdbg.h,v 1.1 2008/06/27 12:49:28 mook Exp $
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above
|
|
||||||
* copyright notice, this list of conditions and the following
|
|
||||||
* disclaimer in the documentation and/or other materials provided
|
|
||||||
* with the distribution.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
|
|
||||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
|
||||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
||||||
* SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* The views and conclusions contained in the software and documentation
|
|
||||||
* are those of the authors and should not be interpreted as representing
|
|
||||||
* official policies, either expressed or implied, of Alacritech, Inc.
|
|
||||||
*
|
|
||||||
**************************************************************************/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FILENAME: sxgdbg.h
|
|
||||||
*
|
|
||||||
* All debug and assertion-based definitions and macros are included
|
|
||||||
* in this file for the SXGOSS driver.
|
|
||||||
*/
|
|
||||||
#ifndef _SXG_DEBUG_H_
|
|
||||||
#define _SXG_DEBUG_H_
|
|
||||||
|
|
||||||
#define ATKDBG 1
|
|
||||||
#define ATK_TRACE_ENABLED 0
|
|
||||||
|
|
||||||
#define DBG_ERROR(n, args...) printk(KERN_WARNING n, ##args)
|
|
||||||
|
|
||||||
#ifdef ASSERT
|
|
||||||
#undef ASSERT
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define SXG_ASSERT_ENABLED
|
|
||||||
#ifdef SXG_ASSERT_ENABLED
|
|
||||||
#ifndef ASSERT
|
|
||||||
#define ASSERT(a) \
|
|
||||||
{ \
|
|
||||||
if (!(a)) { \
|
|
||||||
DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n", \
|
|
||||||
__FILE__, __func__, __LINE__); \
|
|
||||||
} \
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
#ifndef ASSERT
|
|
||||||
#define ASSERT(a)
|
|
||||||
#endif
|
|
||||||
#endif /* SXG_ASSERT_ENABLED */
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef ATKDBG
|
|
||||||
/*
|
|
||||||
* Global for timer granularity; every driver must have an instance
|
|
||||||
* of this initialized to 0
|
|
||||||
*/
|
|
||||||
|
|
||||||
extern ulong ATKTimerDiv;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* trace_entry -
|
|
||||||
*
|
|
||||||
* This structure defines an entry in the trace buffer. The
|
|
||||||
* first few fields mean the same from entry to entry, while
|
|
||||||
* the meaning of last several fields change to suit the
|
|
||||||
* needs of the trace entry. Typically they are function call
|
|
||||||
* parameters.
|
|
||||||
*/
|
|
||||||
struct trace_entry {
|
|
||||||
char name[8];/* 8 character name - like 's'i'm'b'a'r'c'v' */
|
|
||||||
u32 time; /* Current clock tic */
|
|
||||||
unsigned char cpu; /* Current CPU */
|
|
||||||
unsigned char irql; /* Current IRQL */
|
|
||||||
unsigned char driver;/* The driver which added the trace call */
|
|
||||||
/* pad to 4 byte boundary - will probably get used */
|
|
||||||
unsigned char pad2;
|
|
||||||
u32 arg1; /* Caller arg1 */
|
|
||||||
u32 arg2; /* Caller arg2 */
|
|
||||||
u32 arg3; /* Caller arg3 */
|
|
||||||
u32 arg4; /* Caller arg4 */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Driver types for driver field in struct trace_entry */
|
|
||||||
#define TRACE_SXG 1
|
|
||||||
#define TRACE_VPCI 2
|
|
||||||
#define TRACE_SLIC 3
|
|
||||||
|
|
||||||
#define TRACE_ENTRIES 1024
|
|
||||||
|
|
||||||
struct sxg_trace_buffer {
|
|
||||||
/* aid for windbg extension */
|
|
||||||
unsigned int size;
|
|
||||||
unsigned int in; /* Where to add */
|
|
||||||
unsigned int level; /* Current Trace level */
|
|
||||||
spinlock_t lock; /* For MP tracing */
|
|
||||||
struct trace_entry entries[TRACE_ENTRIES];/* The circular buffer */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The trace levels
|
|
||||||
*
|
|
||||||
* XXX At the moment I am only defining critical, important, and noisy.
|
|
||||||
* I am leaving room for more if anyone wants them.
|
|
||||||
*/
|
|
||||||
#define TRACE_NONE 0 /* For trace level - if no tracing wanted */
|
|
||||||
#define TRACE_CRITICAL 1 /* minimal tracing - only critical stuff */
|
|
||||||
#define TRACE_IMPORTANT 5 /* more tracing - anything important */
|
|
||||||
#define TRACE_NOISY 10 /* Everything in the world */
|
|
||||||
|
|
||||||
|
|
||||||
/* The macros themselves */
|
|
||||||
#if ATK_TRACE_ENABLED
|
|
||||||
#define SXG_TRACE_INIT(buffer, tlevel) \
|
|
||||||
{ \
|
|
||||||
memset((buffer), 0, sizeof(struct sxg_trace_buffer)); \
|
|
||||||
(buffer)->level = (tlevel); \
|
|
||||||
(buffer)->size = TRACE_ENTRIES; \
|
|
||||||
spin_lock_init(&(buffer)->lock); \
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define SXG_TRACE_INIT(buffer, tlevel)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*The trace macro. This is active only if ATK_TRACE_ENABLED is set. */
|
|
||||||
#if ATK_TRACE_ENABLED
|
|
||||||
#define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4) { \
|
|
||||||
if ((buffer) && ((buffer)->level >= (tlevel))) { \
|
|
||||||
unsigned int trace_irql = 0;/* ?????? FIX THIS */\
|
|
||||||
unsigned int trace_len; \
|
|
||||||
struct trace_entry *trace_entry; \
|
|
||||||
struct timeval timev; \
|
|
||||||
if(spin_trylock(&(buffer)->lock)) { \
|
|
||||||
trace_entry = &(buffer)->entries[(buffer)->in]; \
|
|
||||||
do_gettimeofday(&timev); \
|
|
||||||
\
|
|
||||||
memset(trace_entry->name, 0, 8); \
|
|
||||||
trace_len = strlen(tname); \
|
|
||||||
trace_len = trace_len > 8 ? 8 : trace_len; \
|
|
||||||
memcpy(trace_entry->name, (tname), trace_len); \
|
|
||||||
trace_entry->time = timev.tv_usec; \
|
|
||||||
trace_entry->cpu = (unsigned char)(smp_processor_id() & 0xFF);\
|
|
||||||
trace_entry->driver = (tdriver); \
|
|
||||||
trace_entry->irql = trace_irql; \
|
|
||||||
trace_entry->arg1 = (ulong)(a1); \
|
|
||||||
trace_entry->arg2 = (ulong)(a2); \
|
|
||||||
trace_entry->arg3 = (ulong)(a3); \
|
|
||||||
trace_entry->arg4 = (ulong)(a4); \
|
|
||||||
\
|
|
||||||
(buffer)->in++; \
|
|
||||||
if ((buffer)->in == TRACE_ENTRIES) \
|
|
||||||
(buffer)->in = 0; \
|
|
||||||
\
|
|
||||||
spin_unlock(&(buffer)->lock); \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _SXG_DEBUG_H_ */
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,130 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright ? 1997-2008 Alacritech, Inc. All rights reserved
|
|
||||||
*
|
|
||||||
* $Id: sxgphycode.h,v 1.2 2008/10/02 01:44:07 Exp $
|
|
||||||
*
|
|
||||||
* sxgphycode.h:
|
|
||||||
*
|
|
||||||
* This file PHY microcode and register initialization data.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**********************************************************************
|
|
||||||
* PHY Microcode
|
|
||||||
**********************************************************************/
|
|
||||||
//
|
|
||||||
// The following contains both PHY microcode and PHY register
|
|
||||||
// initialization data. It is specific to both the PHY and the
|
|
||||||
// type of transceiver.
|
|
||||||
//
|
|
||||||
|
|
||||||
// Download for AEL2005C PHY with SR/LR transceiver (10GBASE-SR or 10GBASE-LR)
|
|
||||||
// AEL2005 SR firmware rev 18 (microInit_mdio_SR_AEL2005C_18.tx).
|
|
||||||
static struct phy_ucode PhyUcode[] = {
|
|
||||||
// NOTE: An address of 0 is a special case. When the download routine
|
|
||||||
// sees an address of 0, it does not write to the PHY. Instead, it delays
|
|
||||||
// the download. The length of the delay (in ms) is given in the data field.
|
|
||||||
// Delays are required at certain points.
|
|
||||||
|
|
||||||
// Platform-specific MDIO Patches:
|
|
||||||
// (include patches for 10G RX polarity flip, 50Mhz Synth, etc)
|
|
||||||
// Addr Data
|
|
||||||
{0xc017, 0xfeb0}, // flip RX_LOS polarity (mandatory patch for SFP+ applications)
|
|
||||||
{0xC001, 0x0428}, // flip RX serial polarity
|
|
||||||
|
|
||||||
{0xc013, 0xf341}, // invert lxmit clock (mandatory patch)
|
|
||||||
{0xc210, 0x8000}, // reset datapath (mandatory patch)
|
|
||||||
{0xc210, 0x8100}, // reset datapath (mandatory patch)
|
|
||||||
{0xc210, 0x8000}, // reset datapath (mandatory patch)
|
|
||||||
{0xc210, 0x0000}, // reset datapath (mandatory patch)
|
|
||||||
{0x0000, 0x0032}, // wait for 50ms for datapath reset to complete. (mandatory patch)
|
|
||||||
|
|
||||||
// Transceiver-specific MDIO Patches:
|
|
||||||
{0xc003, 0x0181}, // (bit 7) enable the CDR inc setting in 1.C005 (mandatory patch for SR code)
|
|
||||||
{0xc010, 0x448a}, // (bit 14) mask out high BER input from the LOS signal in 1.000A (mandatory patch for SR code)
|
|
||||||
|
|
||||||
// Transceiver-specific Microcontroller Initialization:
|
|
||||||
{0xc04a, 0x5200}, // activate microcontroller and pause
|
|
||||||
{0x0000, 0x0032}, // wait 50ms for microcontroller before writing in code.
|
|
||||||
|
|
||||||
// code block starts here:
|
|
||||||
{0xcc00, 0x2ff4}, {0xcc01, 0x3cd4}, {0xcc02, 0x2015}, {0xcc03, 0x3125},
|
|
||||||
{0xcc04, 0x6524}, {0xcc05, 0x27ff}, {0xcc06, 0x300f}, {0xcc07, 0x2c8b},
|
|
||||||
{0xcc08, 0x300b}, {0xcc09, 0x4009}, {0xcc0a, 0x400e}, {0xcc0b, 0x2f12},
|
|
||||||
{0xcc0c, 0x3002}, {0xcc0d, 0x1002}, {0xcc0e, 0x2112}, {0xcc0f, 0x3012},
|
|
||||||
{0xcc10, 0x1002}, {0xcc11, 0x2572}, {0xcc12, 0x3012}, {0xcc13, 0x1002},
|
|
||||||
{0xcc14, 0xd01e}, {0xcc15, 0x2772}, {0xcc16, 0x3012}, {0xcc17, 0x1002},
|
|
||||||
{0xcc18, 0x2004}, {0xcc19, 0x3c84}, {0xcc1a, 0x6436}, {0xcc1b, 0x2007},
|
|
||||||
{0xcc1c, 0x3f87}, {0xcc1d, 0x8676}, {0xcc1e, 0x40b7}, {0xcc1f, 0xa746},
|
|
||||||
{0xcc20, 0x4047}, {0xcc21, 0x5673}, {0xcc22, 0x2982}, {0xcc23, 0x3002},
|
|
||||||
{0xcc24, 0x13d2}, {0xcc25, 0x8bbd}, {0xcc26, 0x2802}, {0xcc27, 0x3012},
|
|
||||||
{0xcc28, 0x1002}, {0xcc29, 0x2032}, {0xcc2a, 0x3012}, {0xcc2b, 0x1002},
|
|
||||||
{0xcc2c, 0x5cc3}, {0xcc2d, 0x0314}, {0xcc2e, 0x2942}, {0xcc2f, 0x3002},
|
|
||||||
{0xcc30, 0x1002}, {0xcc31, 0xd019}, {0xcc32, 0x2fd2}, {0xcc33, 0x3002},
|
|
||||||
{0xcc34, 0x1002}, {0xcc35, 0x2a04}, {0xcc36, 0x3c74}, {0xcc37, 0x6435},
|
|
||||||
{0xcc38, 0x2fa4}, {0xcc39, 0x3cd4}, {0xcc3a, 0x6624}, {0xcc3b, 0x5563},
|
|
||||||
{0xcc3c, 0x2d42}, {0xcc3d, 0x3002}, {0xcc3e, 0x13d2}, {0xcc3f, 0x464d},
|
|
||||||
{0xcc40, 0x2802}, {0xcc41, 0x3012}, {0xcc42, 0x1002}, {0xcc43, 0x2fd2},
|
|
||||||
{0xcc44, 0x3002}, {0xcc45, 0x1002}, {0xcc46, 0x2fb4}, {0xcc47, 0x3cd4},
|
|
||||||
{0xcc48, 0x6624}, {0xcc49, 0x5563}, {0xcc4a, 0x2d42}, {0xcc4b, 0x3002},
|
|
||||||
{0xcc4c, 0x13d2}, {0xcc4d, 0x2e72}, {0xcc4e, 0x3002}, {0xcc4f, 0x1002},
|
|
||||||
{0xcc50, 0x2f72}, {0xcc51, 0x3002}, {0xcc52, 0x1002}, {0xcc53, 0x0004},
|
|
||||||
{0xcc54, 0x2942}, {0xcc55, 0x3002}, {0xcc56, 0x1002}, {0xcc57, 0x2032},
|
|
||||||
{0xcc58, 0x3012}, {0xcc59, 0x1002}, {0xcc5a, 0x5cc3}, {0xcc5b, 0x0317},
|
|
||||||
{0xcc5c, 0x2f12}, {0xcc5d, 0x3002}, {0xcc5e, 0x1002}, {0xcc5f, 0x2942},
|
|
||||||
{0xcc60, 0x3002}, {0xcc61, 0x1002}, {0xcc62, 0x22cd}, {0xcc63, 0x301d},
|
|
||||||
{0xcc64, 0x2802}, {0xcc65, 0x3012}, {0xcc66, 0x1002}, {0xcc67, 0x20b2},
|
|
||||||
{0xcc68, 0x3012}, {0xcc69, 0x1002}, {0xcc6a, 0x5aa3}, {0xcc6b, 0x2dc2},
|
|
||||||
{0xcc6c, 0x3002}, {0xcc6d, 0x1312}, {0xcc6e, 0x2d02}, {0xcc6f, 0x3002},
|
|
||||||
{0xcc70, 0x1002}, {0xcc71, 0x2807}, {0xcc72, 0x31a7}, {0xcc73, 0x20c4},
|
|
||||||
{0xcc74, 0x3c24}, {0xcc75, 0x6724}, {0xcc76, 0x1002}, {0xcc77, 0x2807},
|
|
||||||
{0xcc78, 0x3187}, {0xcc79, 0x20c4}, {0xcc7a, 0x3c24}, {0xcc7b, 0x6724},
|
|
||||||
{0xcc7c, 0x1002}, {0xcc7d, 0x2514}, {0xcc7e, 0x3c64}, {0xcc7f, 0x6436},
|
|
||||||
{0xcc80, 0xdff4}, {0xcc81, 0x6436}, {0xcc82, 0x1002}, {0xcc83, 0x40a4},
|
|
||||||
{0xcc84, 0x643c}, {0xcc85, 0x4016}, {0xcc86, 0x8c6c}, {0xcc87, 0x2b24},
|
|
||||||
{0xcc88, 0x3c24}, {0xcc89, 0x6435}, {0xcc8a, 0x1002}, {0xcc8b, 0x2b24},
|
|
||||||
{0xcc8c, 0x3c24}, {0xcc8d, 0x643a}, {0xcc8e, 0x4025}, {0xcc8f, 0x8a5a},
|
|
||||||
{0xcc90, 0x1002}, {0xcc91, 0x26d1}, {0xcc92, 0x3011}, {0xcc93, 0x1001},
|
|
||||||
{0xcc94, 0xc7a0}, {0xcc95, 0x0100}, {0xcc96, 0xc502}, {0xcc97, 0x53ac},
|
|
||||||
{0xcc98, 0xc503}, {0xcc99, 0xd5d5}, {0xcc9a, 0xc600}, {0xcc9b, 0x2a6d},
|
|
||||||
{0xcc9c, 0xc601}, {0xcc9d, 0x2a4c}, {0xcc9e, 0xc602}, {0xcc9f, 0x0111},
|
|
||||||
{0xcca0, 0xc60c}, {0xcca1, 0x5900}, {0xcca2, 0xc710}, {0xcca3, 0x0700},
|
|
||||||
{0xcca4, 0xc718}, {0xcca5, 0x0700}, {0xcca6, 0xc720}, {0xcca7, 0x4700},
|
|
||||||
{0xcca8, 0xc801}, {0xcca9, 0x7f50}, {0xccaa, 0xc802}, {0xccab, 0x7760},
|
|
||||||
{0xccac, 0xc803}, {0xccad, 0x7fce}, {0xccae, 0xc804}, {0xccaf, 0x5700},
|
|
||||||
{0xccb0, 0xc805}, {0xccb1, 0x5f11}, {0xccb2, 0xc806}, {0xccb3, 0x4751},
|
|
||||||
{0xccb4, 0xc807}, {0xccb5, 0x57e1}, {0xccb6, 0xc808}, {0xccb7, 0x2700},
|
|
||||||
{0xccb8, 0xc809}, {0xccb9, 0x0000}, {0xccba, 0xc821}, {0xccbb, 0x0002},
|
|
||||||
{0xccbc, 0xc822}, {0xccbd, 0x0014}, {0xccbe, 0xc832}, {0xccbf, 0x1186},
|
|
||||||
{0xccc0, 0xc847}, {0xccc1, 0x1e02}, {0xccc2, 0xc013}, {0xccc3, 0xf341},
|
|
||||||
{0xccc4, 0xc01a}, {0xccc5, 0x0446}, {0xccc6, 0xc024}, {0xccc7, 0x1000},
|
|
||||||
{0xccc8, 0xc025}, {0xccc9, 0x0a00}, {0xccca, 0xc026}, {0xcccb, 0x0c0c},
|
|
||||||
{0xcccc, 0xc027}, {0xcccd, 0x0c0c}, {0xccce, 0xc029}, {0xcccf, 0x00a0},
|
|
||||||
{0xccd0, 0xc030}, {0xccd1, 0x0a00}, {0xccd2, 0xc03c}, {0xccd3, 0x001c},
|
|
||||||
{0xccd4, 0xc005}, {0xccd5, 0x7a06}, {0xccd6, 0x0000}, {0xccd7, 0x26d1},
|
|
||||||
{0xccd8, 0x3011}, {0xccd9, 0x1001}, {0xccda, 0xc620}, {0xccdb, 0x0000},
|
|
||||||
{0xccdc, 0xc621}, {0xccdd, 0x003f}, {0xccde, 0xc622}, {0xccdf, 0x0000},
|
|
||||||
{0xcce0, 0xc623}, {0xcce1, 0x0000}, {0xcce2, 0xc624}, {0xcce3, 0x0000},
|
|
||||||
{0xcce4, 0xc625}, {0xcce5, 0x0000}, {0xcce6, 0xc627}, {0xcce7, 0x0000},
|
|
||||||
{0xcce8, 0xc628}, {0xcce9, 0x0000}, {0xccea, 0xc62c}, {0xcceb, 0x0000},
|
|
||||||
{0xccec, 0x0000}, {0xcced, 0x2806}, {0xccee, 0x3cb6}, {0xccef, 0xc161},
|
|
||||||
{0xccf0, 0x6134}, {0xccf1, 0x6135}, {0xccf2, 0x5443}, {0xccf3, 0x0303},
|
|
||||||
{0xccf4, 0x6524}, {0xccf5, 0x000b}, {0xccf6, 0x1002}, {0xccf7, 0x2104},
|
|
||||||
{0xccf8, 0x3c24}, {0xccf9, 0x2105}, {0xccfa, 0x3805}, {0xccfb, 0x6524},
|
|
||||||
{0xccfc, 0xdff4}, {0xccfd, 0x4005}, {0xccfe, 0x6524}, {0xccff, 0x1002},
|
|
||||||
{0xcd00, 0x5dd3}, {0xcd01, 0x0306}, {0xcd02, 0x2ff7}, {0xcd03, 0x38f7},
|
|
||||||
{0xcd04, 0x60b7}, {0xcd05, 0xdffd}, {0xcd06, 0x000a}, {0xcd07, 0x1002},
|
|
||||||
{0xcd08, 0x0000},
|
|
||||||
// end of code block
|
|
||||||
|
|
||||||
// Unpause the microcontroller to start program
|
|
||||||
{0xca00, 0x0080},
|
|
||||||
{0xca12, 0x0000},
|
|
||||||
{0x0000, 0x000A}, // wait 10ms just to be safe
|
|
||||||
|
|
||||||
// Configure the LED's
|
|
||||||
{0xc214, 0x0099}, // configure the LED drivers (for Sahara rev B)
|
|
||||||
{0xc216, 0x0400}, // configure the one LED
|
|
||||||
{0xc217, 0x0000}, // don't drive the 2nd LED (if it exists)
|
|
||||||
|
|
||||||
{0xffff, 0xffff} // table terminator
|
|
||||||
};
|
|
||||||
Loading…
Reference in New Issue
Block a user