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ARM: imx: add ocram clock for imx53

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Add missing ocram gate clock for imx53 and also represent it in device
tree ocram node.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo 2013-07-23 15:56:29 +08:00
parent 951ebf58bf
commit ea257a0328
3 changed files with 4 additions and 1 deletions
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1
Documentation/devicetree/bindings/clock/imx5-clock.txt
View File

@ -197,6 +197,7 @@ clocks and IDs.
spdif0_gate 183 spdif0_gate 183
spdif1_gate 184 spdif1_gate 184
spdif_ipg_gate 185 spdif_ipg_gate 185
ocram 186
Examples (for mx53): Examples (for mx53):

1
arch/arm/boot/dts/imx53.dtsi
View File

@ -1121,6 +1121,7 @@
ocram: sram@f8000000 { ocram: sram@f8000000 {
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0xf8000000 0x20000>; reg = <0xf8000000 0x20000>;
clocks = <&clks 186>;
}; };
}; };
}; };

3
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -119,7 +119,7 @@ enum imx5_clks {
srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
clk_max ocram, clk_max
}; };
static struct clk *clk[clk_max]; static struct clk *clk[clk_max];
@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);