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Second batch of DT changes for 4.3:

Browse Source 
- Add the slow clock to the nodes that will use it
 - Add hlcd to the at91sam9x5 and at91sam9n12
 - Add touchscreen and touch button support to the at91sam9x5ek
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Merge tag 'at91-ab-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/dt

Second batch of DT changes for 4.3:
- Add the slow clock to the nodes that will use it
- Add hlcd to the at91sam9x5 and at91sam9n12
- Add touchscreen and touch button support to the at91sam9x5ek

* tag 'at91-ab-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (22 commits)
  ARM: at91/dt: sama5d2: use slow clock where necessary
  ARM: at91/dt: at91sam9x5dm: add QT1070 touch button controller
  ARM: at91/dt: at91sam9x5dm: add support for the touschscreen
  ARM: at91/dt: add drm support for at91sam9n12ek
  ARM: at91/dt: enable lcd support for at91sam9x5 SoCs
  ARM: at91/dt: add at91sam9x5-ek Display Module dtsi
  ARM: at91/dt: include lcd dtsi in at91sam9x5 dtsis
  ARM: at91/dt: define hlcdc node in at91sam9x5_lcd.dtsi
  ARM: at91/dt: sama5d4: use slow clock where necessary
  ARM: at91/dt: sama5d3: use slow clock where necessary
  ARM: at91/dt: at91sam9x5: use slow clock where necessary
  ARM: at91/dt: at91sam9rl: use slow clock where necessary
  ARM: at91/dt: at91sam9n12: use slow clock where necessary
  ARM: at91/dt: at91sam9g45: use slow clock where necessary
  ARM: at91/dt: at91sam9263: use slow clock where necessary
  ARM: at91/dt: at91sam9261: use slow clock where necessary
  ARM: at91/dt: at91sam9260: use slow clock where necessary
  ARM: at91/dt: at91rm9200: use slow clock where necessary
  Documentation: dt: rtc: at91rm9200: add clocks property
  Documentation: watchdog: at91sam9_wdt: add clocks property
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-08-13 11:58:22 +02:00
commit eb2b508436
24 changed files with 528 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
Documentation/devicetree/bindings/arm/atmel-at91.txt
View File

@ -50,6 +50,7 @@ System Timer (ST) required properties:
- reg: Should contain registers location and length - reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line - interrupts: Should contain interrupt for the ST which is the IRQ line
shared across all System Controller members. shared across all System Controller members.
- clocks: phandle to input clock.
Its subnodes can be: Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt" - watchdog: compatible should be "atmel,at91rm9200-wdt"
@ -61,7 +62,7 @@ TC/TCLIB Timer required properties:
Note that you can specify several interrupt cells if the TC Note that you can specify several interrupt cells if the TC
block has one interrupt per channel. block has one interrupt per channel.
- clock-names: tuple listing input clock names. - clock-names: tuple listing input clock names.
Required elements: "t0_clk" Required elements: "t0_clk", "slow_clk"
Optional elements: "t1_clk", "t2_clk" Optional elements: "t1_clk", "t2_clk"
- clocks: phandles to input clocks. - clocks: phandles to input clocks.
@ -89,12 +90,14 @@ RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc". - compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260" or "at91sam9g45" <chip> can be "at91sam9260" or "at91sam9g45"
- reg: Should contain registers location and length - reg: Should contain registers location and length
- clocks: phandle to input clock.
Example: Example:
rstc@fffffd00 { rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc"; compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
}; };
RAMC SDRAM/DDR Controller required properties: RAMC SDRAM/DDR Controller required properties:
@ -117,6 +120,7 @@ required properties:
- compatible: Should be "atmel,<chip>-shdwc". - compatible: Should be "atmel,<chip>-shdwc".
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length - reg: Should contain registers location and length
- clocks: phandle to input clock.
optional properties: optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode. - atmel,wakeup-mode: String, operation mode of the wakeup mode.
@ -135,9 +139,10 @@ optional at91sam9x5 properties:
Example: Example:
rstc@fffffd00 { shdwc@fffffd10 {
compatible = "atmel,at91sam9260-rstc"; compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
}; };
Special Function Registers (SFR) Special Function Registers (SFR)

2
Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
View File

@ -5,6 +5,7 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
- interrupts: rtc alarm/event interrupt - interrupts: rtc alarm/event interrupt
- clocks: phandle to input clock.
Example: Example:
@ -12,4 +13,5 @@ rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x100>; reg = <0xfffffe00 0x100>;
interrupts = <1 4 7>; interrupts = <1 4 7>;
clocks = <&clk32k>;
}; };

2
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
View File

@ -6,6 +6,7 @@ Required properties:
- compatible: must be "atmel,at91sam9260-wdt". - compatible: must be "atmel,at91sam9260-wdt".
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
- clocks: phandle to input clock.
Optional properties: Optional properties:
- timeout-sec: contains the watchdog timeout in seconds. - timeout-sec: contains the watchdog timeout in seconds.
@ -39,6 +40,7 @@ Example:
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>; reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
timeout-sec = <15>; timeout-sec = <15>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";

10
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -359,6 +359,7 @@
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
reg = <0xfffffd00 0x100>; reg = <0xfffffd00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
watchdog { watchdog {
compatible = "atmel,at91rm9200-wdt"; compatible = "atmel,at91rm9200-wdt";
@ -369,6 +370,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>; reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled"; status = "disabled";
}; };
@ -378,8 +380,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>; 19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
tcb1: timer@fffa4000 { tcb1: timer@fffa4000 {
@ -388,8 +390,8 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>; 22 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
i2c0: i2c@fffb8000 { i2c0: i2c@fffb8000 {

11
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -359,11 +359,13 @@
rstc@fffffd00 { rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc"; compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
}; };
shdwc@fffffd10 { shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc"; compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>; reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fffffd30 { pit: timer@fffffd30 {
@ -379,8 +381,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>; 19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
tcb1: timer@fffdc000 { tcb1: timer@fffdc000 {
@ -389,8 +391,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>; 28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
pinctrl@fffff400 { pinctrl@fffff400 {
@ -973,6 +975,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>; reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";
atmel,dbg-halt; atmel,dbg-halt;

7
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -119,8 +119,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>; <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
usb1: gadget@fffa4000 { usb1: gadget@fffa4000 {
@ -820,11 +820,13 @@
rstc@fffffd00 { rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc"; compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;
}; };
shdwc@fffffd10 { shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc"; compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>; reg = <0xfffffd10 0x10>;
clocks = <&slow_xtal>;
}; };
pit: timer@fffffd30 { pit: timer@fffffd30 {
@ -846,6 +848,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>; reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled"; status = "disabled";
}; };

7
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -377,18 +377,20 @@
compatible = "atmel,at91rm9200-tcb"; compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>; reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>; clocks = <&tcb_clk>, <&slow_xtal>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
rstc@fffffd00 { rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc"; compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;
}; };
shdwc@fffffd10 { shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc"; compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>; reg = <0xfffffd10 0x10>;
clocks = <&slow_xtal>;
}; };
pinctrl@fffff200 { pinctrl@fffff200 {
@ -902,6 +904,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>; reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";
atmel,dbg-halt; atmel,dbg-halt;

1
arch/arm/boot/dts/at91sam9g15.dtsi
View File

@ -7,6 +7,7 @@
*/ */
#include "at91sam9x5.dtsi" #include "at91sam9x5.dtsi"
#include "at91sam9x5_lcd.dtsi"
/ { / {
model = "Atmel AT91SAM9G15 SoC"; model = "Atmel AT91SAM9G15 SoC";

25
arch/arm/boot/dts/at91sam9g15ek.dts
View File

@ -8,9 +8,34 @@
*/ */
/dts-v1/; /dts-v1/;
#include "at91sam9g15.dtsi" #include "at91sam9g15.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi" #include "at91sam9x5ek.dtsi"
/ { / {
model = "Atmel AT91SAM9G15-EK"; model = "Atmel AT91SAM9G15-EK";
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
ahb {
apb {
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
}; };

1
arch/arm/boot/dts/at91sam9g35.dtsi
View File

@ -7,6 +7,7 @@
*/ */
#include "at91sam9x5.dtsi" #include "at91sam9x5.dtsi"
#include "at91sam9x5_lcd.dtsi"
#include "at91sam9x5_macb0.dtsi" #include "at91sam9x5_macb0.dtsi"
/ { / {

21
arch/arm/boot/dts/at91sam9g35ek.dts
View File

@ -8,6 +8,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include "at91sam9g35.dtsi" #include "at91sam9g35.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi" #include "at91sam9x5ek.dtsi"
/ { / {
@ -20,6 +21,26 @@
phy-mode = "rmii"; phy-mode = "rmii";
status = "okay"; status = "okay";
}; };
hlcdc: hlcdc@f8038000 {
status = "okay";
};
}; };
}; };
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
}; };

12
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -387,6 +387,7 @@
rstc@fffffd00 { rstc@fffffd00 {
compatible = "atmel,at91sam9g45-rstc"; compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fffffd30 { pit: timer@fffffd30 {
@ -400,22 +401,23 @@
shdwc@fffffd10 { shdwc@fffffd10 {
compatible = "atmel,at91sam9rl-shdwc"; compatible = "atmel,at91sam9rl-shdwc";
reg = <0xfffffd10 0x10>; reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
}; };
tcb0: timer@fff7c000 { tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb"; compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>; reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
tcb1: timer@fffd4000 { tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb"; compatible = "atmel,at91rm9200-tcb";
reg = <0xfffd4000 0x100>; reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
dma: dma-controller@ffffec00 { dma: dma-controller@ffffec00 {
@ -1123,6 +1125,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>; reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";
atmel,dbg-halt; atmel,dbg-halt;
@ -1257,6 +1260,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffdb0 0x30>; reg = <0xfffffdb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled"; status = "disabled";
}; };

83
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -376,6 +376,7 @@
rstc@fffffe00 { rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc"; compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>; reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fffffe30 { pit: timer@fffffe30 {
@ -388,6 +389,7 @@
shdwc@fffffe10 { shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc"; compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>; reg = <0xfffffe10 0x10>;
clocks = <&clk32k>;
}; };
sckc@fffffe50 { sckc@fffffe50 {
@ -431,16 +433,44 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>; reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>; clocks = <&tcb_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
tcb1: timer@f800c000 { tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>; reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>; clocks = <&tcb_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
};
hlcdc: hlcdc@f8038000 {
compatible = "atmel,at91sam9n12-hlcdc";
reg = <0xf8038000 0x2000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk", "sys_clk", "slow_clk";
status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
}; };
dma: dma-controller@ffffec00 { dma: dma-controller@ffffec00 {
@ -475,6 +505,49 @@
}; };
}; };
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
usart0 { usart0 {
pinctrl_usart0: usart0-0 { pinctrl_usart0: usart0-0 {
atmel,pins = atmel,pins =
@ -891,6 +964,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>; reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";
atmel,dbg-halt; atmel,dbg-halt;
@ -901,6 +975,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>; reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled"; status = "disabled";
}; };

61
arch/arm/boot/dts/at91sam9n12ek.dts
View File

@ -128,6 +128,22 @@
}; };
}; };
hlcdc: hlcdc@f8038000 {
status = "okay";
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
usb1: gadget@f803c000 { usb1: gadget@f803c000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus_sense>; pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
@ -161,6 +177,23 @@
}; };
}; };
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 50000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&bl_reg>;
status = "okay";
};
bl_reg: backlight_regulator {
compatible = "regulator-fixed";
regulator-name = "backlight-power-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "okay";
};
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
@ -194,6 +227,34 @@
}; };
}; };
panel: panel {
compatible = "qd,qd43003c0-40", "simple-panel";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
panel_reg: panel_regulator {
compatible = "regulator-fixed";
regulator-name = "panel-power-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
status = "okay";
};
sound { sound {
compatible = "atmel,asoc-wm8904"; compatible = "atmel,asoc-wm8904";
pinctrl-names = "default"; pinctrl-names = "default";

8
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -121,8 +121,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>, <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>; <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk"; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
}; };
mmc0: mmc@fffa4000 { mmc0: mmc@fffa4000 {
@ -1018,11 +1018,13 @@
rstc@fffffd00 { rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc"; compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>; reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
}; };
shdwc@fffffd10 { shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc"; compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>; reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fffffd30 { pit: timer@fffffd30 {
@ -1036,6 +1038,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>; reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled"; status = "disabled";
}; };
@ -1083,6 +1086,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>; reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled"; status = "disabled";
}; };

1
arch/arm/boot/dts/at91sam9x35.dtsi
View File

@ -7,6 +7,7 @@
*/ */
#include "at91sam9x5.dtsi" #include "at91sam9x5.dtsi"
#include "at91sam9x5_lcd.dtsi"
#include "at91sam9x5_macb0.dtsi" #include "at91sam9x5_macb0.dtsi"
#include "at91sam9x5_can.dtsi" #include "at91sam9x5_can.dtsi"

20
arch/arm/boot/dts/at91sam9x35ek.dts
View File

@ -8,6 +8,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include "at91sam9x35.dtsi" #include "at91sam9x35.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi" #include "at91sam9x5ek.dtsi"
/ { / {
@ -20,6 +21,25 @@
phy-mode = "rmii"; phy-mode = "rmii";
status = "okay"; status = "okay";
}; };
hlcdc: hlcdc@f8038000 {
status = "okay";
};
}; };
}; };
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
}; };

12
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -376,11 +376,13 @@
rstc@fffffe00 { rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc"; compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>; reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
}; };
shdwc@fffffe10 { shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc"; compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>; reg = <0xfffffe10 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fffffe30 { pit: timer@fffffe30 {
@ -418,16 +420,16 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>; reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>; clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
tcb1: timer@f800c000 { tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>; reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>; clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
dma0: dma-controller@ffffec00 { dma0: dma-controller@ffffec00 {
@ -1173,6 +1175,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>; reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";
atmel,dbg-halt; atmel,dbg-halt;
@ -1183,6 +1186,7 @@
compatible = "atmel,at91sam9x5-rtc"; compatible = "atmel,at91sam9x5-rtc";
reg = <0xfffffeb0 0x40>; reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled"; status = "disabled";
}; };

139
arch/arm/boot/dts/at91sam9x5_lcd.dtsi
View File

@ -13,6 +13,137 @@
/ { / {
ahb { ahb {
apb { apb {
hlcdc: hlcdc@f8038000 {
compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
};
pinctrl@fffff400 {
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb444: lcd-rgb-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
};
pinctrl_lcd_rgb565: lcd-rgb-1 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
};
pinctrl_lcd_rgb666: lcd-rgb-2 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
};
pmc: pmc@fffffc00 { pmc: pmc@fffffc00 {
periphck { periphck {
lcdc_clk: lcdc_clk { lcdc_clk: lcdc_clk {
@ -20,6 +151,14 @@
reg = <25>; reg = <25>;
}; };
}; };
systemck {
lcdck: lcdck {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
};
}; };
}; };
}; };

101
arch/arm/boot/dts/at91sam9x5dm.dtsi Normal file
View File

@ -0,0 +1,101 @@
/*
* at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module
*
* Copyright (C) 2014 Atmel,
* 2014 Free Electrons
*
* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
*
* Licensed under GPLv2 or later.
*/
/ {
ahb {
apb {
i2c0: i2c@f8010000 {
qt1070: keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioA>;
interrupts = <7 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
};
hlcdc: hlcdc@f8038000 {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff400 {
board {
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 50000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&bl_reg>;
status = "disabled";
};
bl_reg: backlight_regulator {
compatible = "regulator-fixed";
regulator-name = "backlight-power-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "disabled";
};
panel: panel {
compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
panel_reg: panel_regulator {
compatible = "regulator-fixed";
regulator-name = "panel-power-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};

9
arch/arm/boot/dts/sama5d2.dtsi
View File

@ -764,16 +764,16 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>; reg = <0xf800c000 0x100>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>; clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
tcb1: timer@f8010000 { tcb1: timer@f8010000 {
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8010000 0x100>; reg = <0xf8010000 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb1_clk>; clocks = <&tcb1_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
uart0: serial@f801c000 { uart0: serial@f801c000 {
@ -857,6 +857,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xf80480b0 0x30>; reg = <0xf80480b0 0x30>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
}; };
spi1: spi@fc000000 { spi1: spi@fc000000 {

8
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -145,8 +145,8 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf0010000 0x100>; reg = <0xf0010000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>; clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
i2c0: i2c@f0014000 { i2c0: i2c@f0014000 {
@ -1261,11 +1261,13 @@
rstc@fffffe00 { rstc@fffffe00 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>; reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
}; };
shutdown-controller@fffffe10 { shutdown-controller@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc"; compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>; reg = <0xfffffe10 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fffffe30 { pit: timer@fffffe30 {
@ -1279,6 +1281,7 @@
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>; reg = <0xfffffe40 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
atmel,watchdog-type = "hardware"; atmel,watchdog-type = "hardware";
atmel,reset-type = "all"; atmel,reset-type = "all";
atmel,dbg-halt; atmel,dbg-halt;
@ -1315,6 +1318,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x30>; reg = <0xfffffeb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
}; };
}; };

4
arch/arm/boot/dts/sama5d3_tcb1.dtsi
View File

@ -31,8 +31,8 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8014000 0x100>; reg = <0xf8014000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb1_clk>; clocks = <&tcb1_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
}; };
}; };

12
arch/arm/boot/dts/sama5d4.dtsi
View File

@ -957,8 +957,8 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf801c000 0x100>; reg = <0xf801c000 0x100>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>; clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
macb0: ethernet@f8020000 { macb0: ethernet@f8020000 {
@ -1185,8 +1185,8 @@
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xfc020000 0x100>; reg = <0xfc020000 0x100>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb1_clk>; clocks = <&tcb1_clk>, <&clk32k>;
clock-names = "t0_clk"; clock-names = "t0_clk", "slow_clk";
}; };
adc0: adc@fc034000 { adc0: adc@fc034000 {
@ -1270,11 +1270,13 @@
rstc@fc068600 { rstc@fc068600 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>; reg = <0xfc068600 0x10>;
clocks = <&clk32k>;
}; };
shdwc@fc068610 { shdwc@fc068610 {
compatible = "atmel,at91sam9x5-shdwc"; compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfc068610 0x10>; reg = <0xfc068610 0x10>;
clocks = <&clk32k>;
}; };
pit: timer@fc068630 { pit: timer@fc068630 {
@ -1287,6 +1289,7 @@
watchdog@fc068640 { watchdog@fc068640 {
compatible = "atmel,at91sam9260-wdt"; compatible = "atmel,at91sam9260-wdt";
reg = <0xfc068640 0x10>; reg = <0xfc068640 0x10>;
clocks = <&clk32k>;
status = "disabled"; status = "disabled";
}; };
@ -1320,6 +1323,7 @@
compatible = "atmel,at91rm9200-rtc"; compatible = "atmel,at91rm9200-rtc";
reg = <0xfc0686b0 0x30>; reg = <0xfc0686b0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
}; };
dbgu: serial@fc069000 { dbgu: serial@fc069000 {