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drm/amdgpu: Add unique_id support for sienna cichlid

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This is being added to SMU Metrics, so add the required tie-ins in the
kernel. Also create the corresponding unique_id sysfs file.

v2: Add FW version check, remove SMU mutex
v3: Fix style warning
v4: Add MP1 IP_VERSION check to FW version check

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kent Russell 2022-02-09 19:56:46 -05:00 committed by Alex Deucher
parent 4a93d938a4
commit ebd9c071d2
3 changed files with 45 additions and 2 deletions
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1
drivers/gpu/drm/amd/pm/amdgpu_pm.c
View File

@ -1993,6 +1993,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
case IP_VERSION(10, 3, 0):
*states = ATTR_STATE_SUPPORTED;
break;
default:

13
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
View File

@ -1419,8 +1419,11 @@ typedef struct {
uint8_t PcieRate ;
uint8_t PcieWidth ;
uint16_t AverageGfxclkFrequencyTarget;
uint16_t Padding16_2;
uint32_t PublicSerialNumLower32;
uint32_t PublicSerialNumUpper32;
uint16_t Padding16_2;
} SmuMetrics_t;
typedef struct {
@ -1476,8 +1479,11 @@ typedef struct {
uint8_t PcieRate ;
uint8_t PcieWidth ;
uint16_t AverageGfxclkFrequencyTarget;
uint16_t Padding16_2;
uint32_t PublicSerialNumLower32;
uint32_t PublicSerialNumUpper32;
uint16_t Padding16_2;
} SmuMetrics_V2_t;
typedef struct {
@ -1535,6 +1541,9 @@ typedef struct {
uint8_t PcieWidth;
uint16_t AverageGfxclkFrequencyTarget;
uint32_t PublicSerialNumLower32;
uint32_t PublicSerialNumUpper32;
} SmuMetrics_V3_t;
typedef struct {

33
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -715,6 +715,16 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
*value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
break;
case METRICS_UNIQUE_ID_UPPER32:
*value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 :
use_metrics_v2 ? metrics_v2->PublicSerialNumUpper32 :
metrics->PublicSerialNumUpper32;
break;
case METRICS_UNIQUE_ID_LOWER32:
*value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 :
use_metrics_v2 ? metrics_v2->PublicSerialNumLower32 :
metrics->PublicSerialNumLower32;
break;
default:
*value = UINT_MAX;
break;
@ -1773,6 +1783,28 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu,
return ret;
}
static void sienna_cichlid_get_unique_id(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t upper32 = 0, lower32 = 0;
/* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
if (smu->smc_fw_version < 0x3A5300 ||
smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
return;
if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
goto out;
if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
goto out;
out:
adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
if (adev->serial[0] == '\0')
sprintf(adev->serial, "%016llx", adev->unique_id);
}
static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
{
uint32_t num_discrete_levels = 0;
@ -4182,6 +4214,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_ecc_info = sienna_cichlid_get_ecc_info,
.get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
.set_config_table = sienna_cichlid_set_config_table,
.get_unique_id = sienna_cichlid_get_unique_id,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)