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drm/amd/display: Enable P010 for DCN3x ASICs

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[Why + How]
Enable P010 for SDR video applications.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Stylon Wang 2021-11-12 20:05:19 +08:00 committed by Alex Deucher
parent c022375ae0
commit ebe5ffd8e2
5 changed files with 5 additions and 5 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@ -816,7 +816,7 @@ static const struct dc_plane_cap plane_cap = {
.argb8888 = true,
.nv12 = true,
.fp16 = true,
.p010 = false,
.p010 = true,
.ayuv = false,
},

2
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
View File

@ -656,7 +656,7 @@ static const struct dc_plane_cap plane_cap = {
.argb8888 = true,
.nv12 = true,
.fp16 = true,
.p010 = false,
.p010 = true,
.ayuv = false,
},

2
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
View File

@ -276,7 +276,7 @@ static const struct dc_plane_cap plane_cap = {
.argb8888 = true,
.nv12 = true,
.fp16 = true,
.p010 = false,
.p010 = true,
.ayuv = false,
},
.max_upscale_factor = {

2
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
View File

@ -254,7 +254,7 @@ static const struct dc_plane_cap plane_cap = {
.argb8888 = true,
.nv12 = true,
.fp16 = true,
.p010 = false,
.p010 = true,
.ayuv = false,
},
.max_upscale_factor = {

2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
View File

@ -968,7 +968,7 @@ static const struct dc_plane_cap plane_cap = {
.argb8888 = true,
.nv12 = true,
.fp16 = true,
.p010 = false,
.p010 = true,
.ayuv = false,
},