iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rtw89: 8852c: disable firmware watchdog if CPU disabled

Browse Source 
Disable watchdog timer to prevent it timeout suddenly.

Signed-off-by: Chia-Yuan Li <leo.li@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220408001353.17188-8-pkshih@realtek.com
This commit is contained in:
Chia-Yuan Li 2022-04-08 08:13:47 +08:00 committed by Kalle Valo
parent 1817519701
commit ec356ffb29
3 changed files with 55 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -10,7 +10,7 @@
#include "reg.h"
#include "util.h"
const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_MAX] = {
const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = {
[RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR,
[RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR,
[RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR,
@ -28,8 +28,27 @@ const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_MAX] = {
[RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR,
[RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR,
[RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR,
[RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR,
};
static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
u32 val, enum rtw89_mac_mem_sel sel)
{
u32 addr = rtw89_mac_mem_base_addrs[sel] + offset;
rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);
rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val);
}
static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
enum rtw89_mac_mem_sel sel)
{
u32 addr = rtw89_mac_mem_base_addrs[sel] + offset;
rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);
return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY);
}
int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,
enum rtw89_mac_hwmod_sel sel)
{
@ -2965,6 +2984,19 @@ static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)
return 0;
}
static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
{
u32 val32;
rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL);
val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
val32 |= B_AX_FS_WDT_INT;
val32 &= ~B_AX_FS_WDT_INT_MSK;
rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
}
static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
{
clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
@ -2973,6 +3005,9 @@ static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
rtw89_disable_fw_watchdog(rtwdev);
rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
}

6
drivers/net/wireless/realtek/rtw89/mac.h
View File

@ -245,6 +245,7 @@ enum rtw89_mac_dbg_port_sel {
#define TXD_FIFO_1_BASE_ADDR 0x188A1080
#define TXDATA_FIFO_0_BASE_ADDR 0x18856000
#define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
#define CPU_LOCAL_BASE_ADDR 0x18003000
#define CCTL_INFO_SIZE 32
@ -266,11 +267,10 @@ enum rtw89_mac_mem_sel {
RTW89_MAC_MEM_TXD_FIFO_1,
RTW89_MAC_MEM_TXDATA_FIFO_0,
RTW89_MAC_MEM_TXDATA_FIFO_1,
RTW89_MAC_MEM_CPU_LOCAL,
/* keep last */
RTW89_MAC_MEM_LAST,
RTW89_MAC_MEM_MAX = RTW89_MAC_MEM_LAST,
RTW89_MAC_MEM_INVALID = RTW89_MAC_MEM_LAST,
RTW89_MAC_MEM_NUM,
};
extern const u32 rtw89_mac_mem_base_addrs[];

16
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -3773,4 +3773,20 @@
#define B_IQKINF2_FCNT GENMASK(23, 16)
#define B_IQKINF2_KCNT GENMASK(15, 8)
#define B_IQKINF2_NCTLV GENMAKS(7, 0)
/* WiFi CPU local domain */
#define R_AX_WDT_CTRL 0x0040
#define B_AX_WDT_EN BIT(31)
#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
#define B_AX_IO_HANG_IMR BIT(27)
#define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26)
#define B_AX_IO_HANG_DMAC_EN BIT(25)
#define B_AX_WDT_CLR BIT(16)
#define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
#define WDT_CTRL_ALL_DIS 0
#define R_AX_WDT_STATUS 0x0044
#define B_AX_FS_WDT_INT BIT(8)
#define B_AX_FS_WDT_INT_MSK BIT(0)
#endif