drm/amdgpu/gmc10: program the smallK fragment size
Explicitly set the smallk size to 0 (4k). This is the hw default, but set it anyway just in case something else changed it. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -181,6 +181,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
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WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
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tmp = mmGCVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
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}
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static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
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@ -164,6 +164,10 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
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tmp = mmMMVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
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}
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static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
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