[ARM] 4412/1: S3C2412: reset errata fix
The S3C2412 has an reset-errata where the clock may cause a glitch switching back to EXTCLK. We force a switch to EXTCLK before writing the reset register to force use of the CLKCON sync logic to properly switch. Fix problem reported by Matthieu Castet. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -16,6 +16,7 @@
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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@ -29,6 +30,7 @@
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/idle.h>
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#include <asm/arch/regs-clock.h>
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@ -38,6 +40,7 @@
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#include <asm/arch/regs-gpioj.h>
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#include <asm/arch/regs-dsc.h>
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#include <asm/arch/regs-spi.h>
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#include <asm/arch/regs-s3c2412.h>
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#include <asm/plat-s3c24xx/s3c2412.h>
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#include <asm/plat-s3c24xx/cpu.h>
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@ -106,6 +109,23 @@ static void s3c2412_idle(void)
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cpu_do_idle();
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}
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static void s3c2412_hard_reset(void)
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{
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/* errata "Watch-dog/Software Reset Problem" specifies that
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* this reset must be done with the SYSCLK sourced from
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* EXTCLK instead of FOUT to avoid a glitch in the reset
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* mechanism.
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*
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* See the watchdog section of the S3C2412 manual for more
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* information on this fix.
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*/
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__raw_writel(0x00, S3C2412_CLKSRC);
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__raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
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mdelay(1);
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}
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/* s3c2412_map_io
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*
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* register the standard cpu IO areas, and any passed in from the
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@ -122,6 +142,10 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
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s3c24xx_idle = s3c2412_idle;
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/* set custom reset hook */
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s3c24xx_reset_hook = s3c2412_hard_reset;
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/* register our io-tables */
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iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
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21
include/asm-arm/arch-s3c2410/regs-s3c2412.h
Normal file
21
include/asm-arm/arch-s3c2410/regs-s3c2412.h
Normal file
@ -0,0 +1,21 @@
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/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412.h
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*
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* Copyright 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2412 specific register definitions
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*/
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#ifndef __ASM_ARCH_REGS_S3C2412_H
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#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
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#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
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#define S3C2412_SWRST_RESET (0x533C2412)
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#endif /* __ASM_ARCH_REGS_S3C2412_H */
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