RISC-V Devicetrees for v6.6 Part 2
T-Head: Add a second minimal devicetree for the second board using the th1520 SoC, the BeagleV Ahead. As with the Lichee Pi 4a, this is sufficient only for booting to a console, with work on the mmc, clocks and ethernet sides of things under way. A relicense to a dual licence for the existing devicetree files is also done, for good measure. RISC-V Devicetrees for v6.6-pt2 StarFive: Fix the sort order of some nodes that I resolved incorrectly during a merge conflict. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZOCDsgAKCRB4tDGHoIJi 0mEDAQDc1z032ZsKJSE/WBV0R8hw47RZoP22xHCP3d38vDfP3wEAsF6Kc0U+t8TQ 6CNGHUNpEkVJIdj/wOL8Zk0gV/GdLAA= =F146 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTkE8sACgkQYKtH/8kJ Uido2A//aml2dM6R2eG3Nz5jX0xtAwE5xGix/pHW0eG4Z3c3YFsb6R0cnjO4DLjg MwPrfQl9M7ee2obKsUqOAnD7QgZnP9ewSCOrPqWFn2YKcmA2mZcby4u1qd1m2+Gc UZrvXqoI1ixK4gTxfcfBJI//8ui6AOHMtDvkWlRXCbcMCEruF5NCGNHkDPxve44z 8R/PJUAXEkBUG7mEgnQKTuRgn/Gwgrn0cZKc7YNehAq0SAeihyiRqNNjD/+ftTrl xVrU1RLY/P6dxMP1l3wCxhhM7LPqWSzNflNgAu37A7PmzieYu/FExnW/NuQ3m9UA tzeMGUS4FWkvJKRVwYmzY+SpT4/9SgswUiRoJ6HKCxC63+TMLH6BBJ0HsTFnctq3 mvjqx5kcqe9RVdrJBPSbYuH7xdbvWD2I+m7IQnuOvkwPghRuBf2q6HQ2L2ah7WlJ ZOcJ82/kUx/Cb5o0hDMvKVfU+ZUGoDPWKfqpqVfftgh5TTOoZpmMfMclwSG2zw3/ PoXLE+dnYCBtynAYAbX/Z5YPIdV3WL5/TJEAVIgyFBKPcUsi0Hc841gkymur1lCr fd+scjRCON1zV3EILI/CDEwXToyVlPqMSznjj+nm3sV05tCUA1GQ8I/RsnwbFSsP /gNtPJ9fJRKtfTrU7lLdaaauk+aoRvRud3XQpwYmCfWLCDJ+ciQ= =3ypd -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6 Part 2 T-Head: Add a second minimal devicetree for the second board using the th1520 SoC, the BeagleV Ahead. As with the Lichee Pi 4a, this is sufficient only for booting to a console, with work on the mmc, clocks and ethernet sides of things under way. A relicense to a dual licence for the existing devicetree files is also done, for good measure. RISC-V Devicetrees for v6.6-pt2 StarFive: Fix the sort order of some nodes that I resolved incorrectly during a merge conflict. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles riscv: dts: starfive: fix jh7110 qspi sort order Link: https://lore.kernel.org/r/20230819-unwieldy-railing-9bba2b176aa7@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ecd2dc2f34
@ -17,6 +17,10 @@ properties:
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const: '/'
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compatible:
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oneOf:
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- description: BeagleV Ahead single board computer
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items:
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- const: beagle,beaglev-ahead
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- const: thead,th1520
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- description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
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items:
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- enum:
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@ -676,25 +676,6 @@
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status = "disabled";
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};
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qspi: spi@13010000 {
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compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
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reg = <0x0 0x13010000 0x0 0x10000>,
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<0x0 0x21000000 0x0 0x400000>;
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interrupts = <25>;
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clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
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<&syscrg JH7110_SYSCLK_QSPI_AHB>,
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<&syscrg JH7110_SYSCLK_QSPI_APB>;
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clock-names = "ref", "ahb", "apb";
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resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
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<&syscrg JH7110_SYSRST_QSPI_AHB>,
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<&syscrg JH7110_SYSRST_QSPI_REF>;
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reset-names = "qspi", "qspi-ocp", "rstc_ref";
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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status = "disabled";
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};
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spi3: spi@12070000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x0 0x12070000 0x0 0x10000>;
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@ -767,6 +748,25 @@
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#thermal-sensor-cells = <0>;
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};
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qspi: spi@13010000 {
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compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
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reg = <0x0 0x13010000 0x0 0x10000>,
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<0x0 0x21000000 0x0 0x400000>;
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interrupts = <25>;
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clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
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<&syscrg JH7110_SYSCLK_QSPI_AHB>,
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<&syscrg JH7110_SYSCLK_QSPI_APB>;
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clock-names = "ref", "ahb", "apb";
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resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
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<&syscrg JH7110_SYSRST_QSPI_AHB>,
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<&syscrg JH7110_SYSRST_QSPI_REF>;
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reset-names = "qspi", "qspi-ocp", "rstc_ref";
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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status = "disabled";
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};
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syscrg: clock-controller@13020000 {
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compatible = "starfive,jh7110-syscrg";
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reg = <0x0 0x13020000 0x0 0x10000>;
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@ -1,2 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
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dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb
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61
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
Normal file
61
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
Normal file
@ -0,0 +1,61 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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* Copyright (C) 2023 Drew Fustini <dfustini@baylibre.com>
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*/
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/dts-v1/;
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#include "th1520.dtsi"
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/ {
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model = "BeagleV Ahead";
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compatible = "beagle,beaglev-ahead", "thead,th1520";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x1 0x00000000>;
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};
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};
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&osc {
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clock-frequency = <24000000>;
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};
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&osc_32k {
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clock-frequency = <32768>;
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};
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&apb_clk {
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clock-frequency = <62500000>;
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};
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&uart_sclk {
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clock-frequency = <100000000>;
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};
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&dmac0 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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