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Merge remote branch 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next into drm-linus

Browse Source 
* 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next:
  drm/nouveau: remove use of -ERESTART
  nouveau: Fix endianness with new context program loader
  drm/nouveau: fix build with CONFIG_AGP=n
  drm/nouveau: fix ch7006 build
This commit is contained in:
Dave Airlie 2009-12-16 15:52:21 +10:00
commit ece84e04e9
6 changed files with 22 additions and 18 deletions
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5
drivers/gpu/drm/nouveau/Kconfig
View File

@ -30,11 +30,12 @@ config DRM_NOUVEAU_DEBUG
via debugfs.
menu "I2C encoder or helper chips"
depends on DRM
depends on DRM && I2C
config DRM_I2C_CH7006
tristate "Chrontel ch7006 TV encoder"
default m if DRM_NOUVEAU
depends on DRM_NOUVEAU
default m
help
Support for Chrontel ch7006 and similar TV encoders, found
on some nVidia video cards.

2
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -311,8 +311,10 @@ nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
struct drm_device *dev = dev_priv->dev;
switch (dev_priv->gart_info.type) {
#if __OS_HAS_AGP
case NOUVEAU_GART_AGP:
return ttm_agp_backend_init(bdev, dev->agp->bridge);
#endif
case NOUVEAU_GART_SGDMA:
return nouveau_sgdma_init_ttm(dev);
default:

2
drivers/gpu/drm/nouveau/nouveau_fence.c
View File

@ -205,7 +205,7 @@ nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
schedule_timeout(1);
if (intr && signal_pending(current)) {
ret = -ERESTART;
ret = -ERESTARTSYS;
break;
}
}

7
drivers/gpu/drm/nouveau/nouveau_gem.c
View File

@ -342,8 +342,6 @@ retry:
}
ret = ttm_bo_wait_cpu(&nvbo->bo, false);
if (ret == -ERESTART)
ret = -EAGAIN;
if (ret)
return ret;
goto retry;
@ -915,8 +913,6 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
goto out;
ret = ttm_bo_wait_cpu(&nvbo->bo, no_wait);
if (ret == -ERESTART)
ret = -EAGAIN;
if (ret)
goto out;
}
@ -925,9 +921,6 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait);
} else {
ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait);
if (ret == -ERESTART)
ret = -EAGAIN;
else
if (ret == 0)
nvbo->cpu_filp = file_priv;
}

4
drivers/gpu/drm/nouveau/nouveau_mem.c
View File

@ -407,6 +407,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
return 0;
}
#if __OS_HAS_AGP
static void nouveau_mem_reset_agp(struct drm_device *dev)
{
uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
@ -432,10 +433,12 @@ static void nouveau_mem_reset_agp(struct drm_device *dev)
nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
}
#endif
int
nouveau_mem_init_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct drm_agp_info info;
struct drm_agp_mode mode;
@ -471,6 +474,7 @@ nouveau_mem_init_agp(struct drm_device *dev)
dev_priv->gart_info.type = NOUVEAU_GART_AGP;
dev_priv->gart_info.aper_base = info.aperture_base;
dev_priv->gart_info.aper_size = info.aperture_size;
#endif
return 0;
}

20
drivers/gpu/drm/nouveau/nv40_graph.c
View File

@ -252,8 +252,9 @@ nv40_grctx_init(struct drm_device *dev)
memcpy(pgraph->ctxprog, fw->data, fw->size);
cp = pgraph->ctxprog;
if (cp->signature != 0x5043564e || cp->version != 0 ||
cp->length != ((fw->size - 7) / 4)) {
if (le32_to_cpu(cp->signature) != 0x5043564e ||
cp->version != 0 ||
le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
NV_ERROR(dev, "ctxprog invalid\n");
release_firmware(fw);
nv40_grctx_fini(dev);
@ -281,8 +282,9 @@ nv40_grctx_init(struct drm_device *dev)
memcpy(pgraph->ctxvals, fw->data, fw->size);
cv = (void *)pgraph->ctxvals;
if (cv->signature != 0x5643564e || cv->version != 0 ||
cv->length != ((fw->size - 9) / 8)) {
if (le32_to_cpu(cv->signature) != 0x5643564e ||
cv->version != 0 ||
le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
NV_ERROR(dev, "ctxvals invalid\n");
release_firmware(fw);
nv40_grctx_fini(dev);
@ -294,8 +296,9 @@ nv40_grctx_init(struct drm_device *dev)
cp = pgraph->ctxprog;
nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
for (i = 0; i < cp->length; i++)
nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp->data[i]);
for (i = 0; i < le16_to_cpu(cp->length); i++)
nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
le32_to_cpu(cp->data[i]));
pgraph->accel_blocked = false;
return 0;
@ -329,8 +332,9 @@ nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
if (!cv)
return;
for (i = 0; i < cv->length; i++)
nv_wo32(dev, ctx, cv->data[i].offset, cv->data[i].value);
for (i = 0; i < le32_to_cpu(cv->length); i++)
nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
le32_to_cpu(cv->data[i].value));
}
/*