dmaengine: idxd: Remove shadow Event Log head stored in idxd
head is defined in idxd->evl as a shadow of head in the EVLSTATUS register. There are two issues related to the shadow head: 1. Mismatch between the shadow head and the state of the EVLSTATUS register: If Event Log is supported, upon completion of the Enable Device command, the Event Log head in the variable idxd->evl->head should be cleared to match the state of the EVLSTATUS register. But the variable is not reset currently, leading mismatch between the variable and the register state. The mismatch causes incorrect processing of Event Log entries. 2. Unnecessary shadow head definition: The shadow head is unnecessary as head can be read directly from the EVLSTATUS register. Reading head from the register incurs no additional cost because event log head and tail are always read together and tail is already read directly from the register as required by hardware. Remove the shadow Event Log head stored in idxd->evl to address the mentioned issues. Fixes: 244da66cda35 ("dmaengine: idxd: setup event log configuration") Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20240215024931.1739621-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -345,7 +345,7 @@ static void idxd_cdev_evl_drain_pasid(struct idxd_wq *wq, u32 pasid)
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spin_lock(&evl->lock);
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status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
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t = status.tail;
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h = evl->head;
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h = status.head;
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size = evl->size;
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while (h != t) {
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@ -68,9 +68,9 @@ static int debugfs_evl_show(struct seq_file *s, void *d)
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spin_lock(&evl->lock);
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h = evl->head;
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evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
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t = evl_status.tail;
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h = evl_status.head;
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evl_size = evl->size;
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seq_printf(s, "Event Log head %u tail %u interrupt pending %u\n\n",
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@ -300,7 +300,6 @@ struct idxd_evl {
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unsigned int log_size;
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/* The number of entries in the event log. */
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u16 size;
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u16 head;
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unsigned long *bmap;
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bool batch_fail[IDXD_MAX_BATCH_IDENT];
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};
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@ -367,9 +367,9 @@ static void process_evl_entries(struct idxd_device *idxd)
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/* Clear interrupt pending bit */
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iowrite32(evl_status.bits_upper32,
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idxd->reg_base + IDXD_EVLSTATUS_OFFSET + sizeof(u32));
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h = evl->head;
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evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
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t = evl_status.tail;
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h = evl_status.head;
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size = idxd->evl->size;
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while (h != t) {
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@ -378,7 +378,6 @@ static void process_evl_entries(struct idxd_device *idxd)
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h = (h + 1) % size;
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}
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evl->head = h;
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evl_status.head = h;
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iowrite32(evl_status.bits_lower32, idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
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spin_unlock(&evl->lock);
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