ipc: Added support for IPC interrupt mode
This patch adds support for ipc command interrupt mode. Also added platform data option to select 'irq_mode' irq_mode = 1: configure the driver to receive IOC interrupt for each successful ipc_command. irq_mode = 0: makes driver use polling method to track the command completion status. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
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@ -60,6 +60,7 @@
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#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
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#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
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#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
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#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
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#define IPC_IOC 0x100 /* IPC command register IOC bit */
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enum {
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enum {
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SCU_IPC_LINCROFT,
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SCU_IPC_LINCROFT,
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@ -74,6 +75,7 @@ struct intel_scu_ipc_pdata_t {
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u32 i2c_base;
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u32 i2c_base;
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u32 ipc_len;
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u32 ipc_len;
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u32 i2c_len;
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u32 i2c_len;
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u8 irq_mode;
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};
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};
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static struct intel_scu_ipc_pdata_t intel_scu_ipc_pdata[] = {
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static struct intel_scu_ipc_pdata_t intel_scu_ipc_pdata[] = {
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@ -82,24 +84,28 @@ static struct intel_scu_ipc_pdata_t intel_scu_ipc_pdata[] = {
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.i2c_base = 0xff12b000,
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.i2c_base = 0xff12b000,
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.ipc_len = 0x100,
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.ipc_len = 0x100,
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.i2c_len = 0x10,
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.i2c_len = 0x10,
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.irq_mode = 0,
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},
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},
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[SCU_IPC_PENWELL] = {
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[SCU_IPC_PENWELL] = {
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.ipc_base = 0xff11c000,
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.ipc_base = 0xff11c000,
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.i2c_base = 0xff12b000,
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.i2c_base = 0xff12b000,
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.ipc_len = 0x100,
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.ipc_len = 0x100,
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.i2c_len = 0x10,
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.i2c_len = 0x10,
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.irq_mode = 1,
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},
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},
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[SCU_IPC_CLOVERVIEW] = {
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[SCU_IPC_CLOVERVIEW] = {
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.ipc_base = 0xff11c000,
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.ipc_base = 0xff11c000,
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.i2c_base = 0xff12b000,
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.i2c_base = 0xff12b000,
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.ipc_len = 0x100,
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.ipc_len = 0x100,
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.i2c_len = 0x10,
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.i2c_len = 0x10,
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.irq_mode = 1,
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},
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},
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[SCU_IPC_TANGIER] = {
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[SCU_IPC_TANGIER] = {
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.ipc_base = 0xff009000,
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.ipc_base = 0xff009000,
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.i2c_base = 0xff00d000,
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.i2c_base = 0xff00d000,
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.ipc_len = 0x100,
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.ipc_len = 0x100,
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.i2c_len = 0x10,
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.i2c_len = 0x10,
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.irq_mode = 0,
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},
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},
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};
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};
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@ -110,6 +116,8 @@ struct intel_scu_ipc_dev {
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struct pci_dev *pdev;
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struct pci_dev *pdev;
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void __iomem *ipc_base;
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void __iomem *ipc_base;
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void __iomem *i2c_base;
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void __iomem *i2c_base;
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struct completion cmd_complete;
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u8 irq_mode;
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};
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};
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static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
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static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
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@ -136,6 +144,10 @@ static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
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*/
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*/
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static inline void ipc_command(u32 cmd) /* Send ipc command */
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static inline void ipc_command(u32 cmd) /* Send ipc command */
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{
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{
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if (ipcdev.irq_mode) {
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reinit_completion(&ipcdev.cmd_complete);
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writel(cmd | IPC_IOC, ipcdev.ipc_base);
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}
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writel(cmd, ipcdev.ipc_base);
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writel(cmd, ipcdev.ipc_base);
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}
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}
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@ -194,6 +206,30 @@ static inline int busy_loop(void) /* Wait till scu status is busy */
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return 0;
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return 0;
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}
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}
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/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
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static inline int ipc_wait_for_interrupt(void)
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{
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int status;
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if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) {
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struct device *dev = &ipcdev.pdev->dev;
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dev_err(dev, "IPC timed out\n");
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return -ETIMEDOUT;
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}
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status = ipc_read_status();
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if ((status >> 1) & 1)
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return -EIO;
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return 0;
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}
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int intel_scu_ipc_check_status(void)
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{
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return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop();
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}
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/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
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/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
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static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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{
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{
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@ -234,7 +270,7 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
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ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
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}
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}
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err = busy_loop();
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err = intel_scu_ipc_check_status();
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if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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/* Workaround: values are read as 0 without memcpy_fromio */
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/* Workaround: values are read as 0 without memcpy_fromio */
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memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
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memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
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@ -429,7 +465,7 @@ int intel_scu_ipc_simple_command(int cmd, int sub)
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return -ENODEV;
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return -ENODEV;
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}
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}
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ipc_command(sub << 12 | cmd);
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ipc_command(sub << 12 | cmd);
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err = busy_loop();
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err = intel_scu_ipc_check_status();
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mutex_unlock(&ipclock);
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mutex_unlock(&ipclock);
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return err;
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return err;
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}
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}
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@ -463,7 +499,7 @@ int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
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ipc_data_writel(*in++, 4 * i);
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ipc_data_writel(*in++, 4 * i);
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ipc_command((inlen << 16) | (sub << 12) | cmd);
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ipc_command((inlen << 16) | (sub << 12) | cmd);
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err = busy_loop();
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err = intel_scu_ipc_check_status();
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if (!err) {
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if (!err) {
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for (i = 0; i < outlen; i++)
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for (i = 0; i < outlen; i++)
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@ -531,6 +567,9 @@ EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
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*/
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*/
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static irqreturn_t ioc(int irq, void *dev_id)
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static irqreturn_t ioc(int irq, void *dev_id)
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{
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{
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if (ipcdev.irq_mode)
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complete(&ipcdev.cmd_complete);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -555,6 +594,7 @@ static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
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pdata = &intel_scu_ipc_pdata[pid];
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pdata = &intel_scu_ipc_pdata[pid];
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ipcdev.pdev = pci_dev_get(dev);
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ipcdev.pdev = pci_dev_get(dev);
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ipcdev.irq_mode = pdata->irq_mode;
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err = pci_enable_device(dev);
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err = pci_enable_device(dev);
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if (err)
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if (err)
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@ -568,6 +608,8 @@ static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
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if (!pci_resource)
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if (!pci_resource)
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return -ENOMEM;
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return -ENOMEM;
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init_completion(&ipcdev.cmd_complete);
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if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
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if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
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return -EBUSY;
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return -EBUSY;
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