drm/amd/display: Update watermark values for DCN301
[ Upstream commit 2d8ae25d233767171942a9fba5fd8f4a620996be ] [Why] There is underflow / visual corruption DCN301, for high bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60. [How] Use up-to-date watermark values for DCN301. Reviewed-by: Zhan Liu <zhan.liu@amd.com> Signed-off-by: Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -582,32 +582,32 @@ static struct wm_table lpddr5_wm_table = {
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 7.95,
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.sr_enter_plus_exit_time_us = 9,
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.sr_exit_time_us = 13.5,
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.sr_enter_plus_exit_time_us = 16.5,
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.valid = true,
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},
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 9.82,
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.sr_enter_plus_exit_time_us = 11.196,
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.sr_exit_time_us = 13.5,
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.sr_enter_plus_exit_time_us = 16.5,
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.valid = true,
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},
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 9.89,
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.sr_enter_plus_exit_time_us = 11.24,
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.sr_exit_time_us = 13.5,
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.sr_enter_plus_exit_time_us = 16.5,
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.valid = true,
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},
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 9.748,
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.sr_enter_plus_exit_time_us = 11.102,
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.sr_exit_time_us = 13.5,
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.sr_enter_plus_exit_time_us = 16.5,
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.valid = true,
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},
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}
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