interconnect: qcom: sm8350: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-19-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Konrad Dybcio
Georgi Djakov
parent
8e509d66df
commit
edd13c04ff
@ -1354,38 +1354,282 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
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.links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
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};
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DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
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DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
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DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
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DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc);
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DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
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DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
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DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
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DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
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DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
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DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
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DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf);
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DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot);
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DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
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DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
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DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
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DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
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DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
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DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
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DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
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DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
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DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0);
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DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1);
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DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
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DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
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DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
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DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp);
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DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp);
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DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp);
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DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp);
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DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp);
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DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp);
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DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp);
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static struct qcom_icc_bcm bcm_acv = {
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.name = "ACV",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &ebi },
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};
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static struct qcom_icc_bcm bcm_ce0 = {
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.name = "CE0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxm_crypto },
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};
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static struct qcom_icc_bcm bcm_cn0 = {
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.name = "CN0",
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.keepalive = true,
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.num_nodes = 2,
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.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
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};
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static struct qcom_icc_bcm bcm_cn1 = {
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.name = "CN1",
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.keepalive = false,
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.num_nodes = 47,
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.nodes = { &xm_qdss_dap,
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&qhs_ahb2phy0,
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&qhs_ahb2phy1,
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&qhs_aoss,
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&qhs_apss,
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&qhs_camera_cfg,
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&qhs_clk_ctl,
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&qhs_compute_cfg,
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&qhs_cpr_cx,
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&qhs_cpr_mmcx,
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&qhs_cpr_mx,
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&qhs_crypto0_cfg,
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&qhs_cx_rdpm,
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&qhs_dcc_cfg,
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&qhs_display_cfg,
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&qhs_gpuss_cfg,
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&qhs_hwkm,
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&qhs_imem_cfg,
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&qhs_ipa,
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&qhs_ipc_router,
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&qhs_mss_cfg,
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&qhs_mx_rdpm,
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&qhs_pcie0_cfg,
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&qhs_pcie1_cfg,
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&qhs_pimem_cfg,
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&qhs_pka_wrapper_cfg,
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&qhs_pmu_wrapper_cfg,
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&qhs_qdss_cfg,
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&qhs_qup0,
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&qhs_qup1,
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&qhs_qup2,
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&qhs_security,
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&qhs_spss_cfg,
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&qhs_tcsr,
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&qhs_tlmm,
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&qhs_ufs_card_cfg,
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&qhs_ufs_mem_cfg,
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&qhs_usb3_0,
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&qhs_usb3_1,
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&qhs_venus_cfg,
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&qhs_vsense_ctrl_cfg,
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&qns_a1_noc_cfg,
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&qns_a2_noc_cfg,
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&qns_ddrss_cfg,
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&qns_mnoc_cfg,
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&qns_snoc_cfg,
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&srvc_cnoc
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},
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};
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static struct qcom_icc_bcm bcm_cn2 = {
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.name = "CN2",
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.keepalive = false,
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.num_nodes = 5,
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.nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 },
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};
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static struct qcom_icc_bcm bcm_co0 = {
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.name = "CO0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_nsp_gemnoc },
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};
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static struct qcom_icc_bcm bcm_co3 = {
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.name = "CO3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxm_nsp },
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};
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static struct qcom_icc_bcm bcm_mc0 = {
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.name = "MC0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &ebi },
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};
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static struct qcom_icc_bcm bcm_mm0 = {
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.name = "MM0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_hf },
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};
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static struct qcom_icc_bcm bcm_mm1 = {
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.name = "MM1",
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.keepalive = false,
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.num_nodes = 3,
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.nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
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};
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static struct qcom_icc_bcm bcm_mm4 = {
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.name = "MM4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_sf },
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};
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static struct qcom_icc_bcm bcm_mm5 = {
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.name = "MM5",
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.keepalive = false,
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.num_nodes = 6,
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.nodes = { &qnm_camnoc_icp,
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&qnm_camnoc_sf,
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&qnm_video0,
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&qnm_video1,
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&qnm_video_cvp,
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&qxm_rot
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},
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};
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static struct qcom_icc_bcm bcm_sh0 = {
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.name = "SH0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_llcc },
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};
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static struct qcom_icc_bcm bcm_sh2 = {
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.name = "SH2",
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.keepalive = false,
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.num_nodes = 2,
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.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
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};
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static struct qcom_icc_bcm bcm_sh3 = {
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.name = "SH3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_cmpnoc },
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};
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static struct qcom_icc_bcm bcm_sh4 = {
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.name = "SH4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &chm_apps },
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};
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static struct qcom_icc_bcm bcm_sn0 = {
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.name = "SN0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_gemnoc_sf },
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};
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static struct qcom_icc_bcm bcm_sn2 = {
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.name = "SN2",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_gemnoc_gc },
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};
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static struct qcom_icc_bcm bcm_sn3 = {
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.name = "SN3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxs_pimem },
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};
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static struct qcom_icc_bcm bcm_sn4 = {
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.name = "SN4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &xs_qdss_stm },
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};
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static struct qcom_icc_bcm bcm_sn5 = {
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.name = "SN5",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &xm_pcie3_0 },
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};
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static struct qcom_icc_bcm bcm_sn6 = {
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.name = "SN6",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &xm_pcie3_1 },
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};
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static struct qcom_icc_bcm bcm_sn7 = {
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.name = "SN7",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_aggre1_noc },
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};
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static struct qcom_icc_bcm bcm_sn8 = {
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.name = "SN8",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_aggre2_noc },
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};
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static struct qcom_icc_bcm bcm_sn14 = {
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.name = "SN14",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_pcie_mem_noc },
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};
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static struct qcom_icc_bcm bcm_acv_disp = {
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.name = "ACV",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &ebi_disp },
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};
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static struct qcom_icc_bcm bcm_mc0_disp = {
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.name = "MC0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &ebi_disp },
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};
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static struct qcom_icc_bcm bcm_mm0_disp = {
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.name = "MM0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_hf_disp },
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};
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static struct qcom_icc_bcm bcm_mm1_disp = {
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.name = "MM1",
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.keepalive = false,
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.num_nodes = 2,
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.nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp },
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};
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static struct qcom_icc_bcm bcm_mm4_disp = {
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.name = "MM4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_sf_disp },
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};
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static struct qcom_icc_bcm bcm_mm5_disp = {
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.name = "MM5",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxm_rot_disp },
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};
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static struct qcom_icc_bcm bcm_sh0_disp = {
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.name = "SH0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_llcc_disp },
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};
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static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
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};
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