libata: add new driver pdc_adma for PDC ADMA ATA cards
This commit is contained in:
Mark Lord
Jeff Garzik
parent
3d3467f0fd
commit
edea3ab58f
@ -489,11 +489,11 @@ config SCSI_SATA_NV
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If unsure, say N.
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config SCSI_SATA_PROMISE
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tristate "Promise SATA TX2/TX4 support"
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config SCSI_PDC_ADMA
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tristate "Pacific Digital ADMA support"
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depends on SCSI_SATA && PCI
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help
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This option enables support for Promise Serial ATA TX2/TX4.
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This option enables support for Pacific Digital ADMA controllers
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If unsure, say N.
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@ -505,6 +505,14 @@ config SCSI_SATA_QSTOR
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If unsure, say N.
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config SCSI_SATA_PROMISE
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tristate "Promise SATA TX2/TX4 support"
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depends on SCSI_SATA && PCI
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help
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This option enables support for Promise Serial ATA TX2/TX4.
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If unsure, say N.
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config SCSI_SATA_SX4
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tristate "Promise SATA SX4 support"
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depends on SCSI_SATA && PCI && EXPERIMENTAL
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@ -138,6 +138,7 @@ obj-$(CONFIG_SCSI_SATA_SX4) += libata.o sata_sx4.o
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obj-$(CONFIG_SCSI_SATA_NV) += libata.o sata_nv.o
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obj-$(CONFIG_SCSI_SATA_ULI) += libata.o sata_uli.o
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obj-$(CONFIG_SCSI_SATA_MV) += libata.o sata_mv.o
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obj-$(CONFIG_SCSI_PDC_ADMA) += libata.o pdc_adma.o
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obj-$(CONFIG_ARM) += arm/
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737
drivers/scsi/pdc_adma.c
Normal file
737
drivers/scsi/pdc_adma.c
Normal file
@ -0,0 +1,737 @@
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/*
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* pdc_adma.c - Pacific Digital Corporation ADMA
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*
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* Maintained by: Mark Lord <mlord@pobox.com>
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*
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* Copyright 2005 Mark Lord
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*
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* The contents of this file are subject to the Open
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* Software License version 1.1 that can be found at
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* http://www.opensource.org/licenses/osl-1.1.txt and is included herein
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* by reference.
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the GNU General Public License version 2 (the "GPL") as distributed
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* in the kernel source COPYING file, in which case the provisions of
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* the GPL are applicable instead of the above. If you wish to allow
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* the use of your version of this file only under the terms of the
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* GPL and not to allow others to use your version of this file under
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* the OSL, indicate your decision by deleting the provisions above and
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* replace them with the notice and other provisions required by the GPL.
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* If you do not delete the provisions above, a recipient may use your
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* version of this file under either the OSL or the GPL.
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*
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* Supports ATA disks in single-packet ADMA mode.
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* Uses PIO for everything else.
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*
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* TODO: Use ADMA transfers for ATAPI devices, when possible.
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* This requires careful attention to a number of quirks of the chip.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include <asm/io.h>
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#include <linux/libata.h>
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#define DRV_NAME "pdc_adma"
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#define DRV_VERSION "0.01"
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/* macro to calculate base address for ATA regs */
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#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
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/* macro to calculate base address for ADMA regs */
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#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
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enum {
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ADMA_PORTS = 2,
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ADMA_CPB_BYTES = 40,
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ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
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ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
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ADMA_DMA_BOUNDARY = 0xffffffff,
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/* global register offsets */
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ADMA_MODE_LOCK = 0x00c7,
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/* per-channel register offsets */
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ADMA_CONTROL = 0x0000, /* ADMA control */
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ADMA_STATUS = 0x0002, /* ADMA status */
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ADMA_CPB_COUNT = 0x0004, /* CPB count */
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ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
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ADMA_CPB_NEXT = 0x000c, /* next CPB address */
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ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
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ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
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ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
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/* ADMA_CONTROL register bits */
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aNIEN = (1 << 8), /* irq mask: 1==masked */
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aGO = (1 << 7), /* packet trigger ("Go!") */
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aRSTADM = (1 << 5), /* ADMA logic reset */
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aAUTEN = (1 << 3), /* packet trigger ("Go!") */
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aRSTA = (1 << 2), /* ATA hard reset */
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aPIOMD4 = 0x0003, /* PIO mode 4 */
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/* ADMA_STATUS register bits */
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aPSD = (1 << 6),
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aUIRQ = (1 << 4),
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aPERR = (1 << 0),
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/* CPB bits */
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cDONE = (1 << 0),
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cVLD = (1 << 0),
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cDAT = (1 << 2),
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cIEN = (1 << 3),
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/* PRD bits */
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pORD = (1 << 4),
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pDIRO = (1 << 5),
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pEND = (1 << 7),
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/* ATA register flags */
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rIGN = (1 << 5),
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rEND = (1 << 7),
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/* ATA register addresses */
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ADMA_REGS_CONTROL = 0x0e,
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ADMA_REGS_SECTOR_COUNT = 0x12,
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ADMA_REGS_LBA_LOW = 0x13,
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ADMA_REGS_LBA_MID = 0x14,
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ADMA_REGS_LBA_HIGH = 0x15,
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ADMA_REGS_DEVICE = 0x16,
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ADMA_REGS_COMMAND = 0x17,
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/* PCI device IDs */
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board_1841_idx = 0, /* ADMA 2-port controller */
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};
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typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
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struct adma_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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adma_state_t state;
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};
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static int adma_ata_init_one (struct pci_dev *pdev,
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const struct pci_device_id *ent);
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static irqreturn_t adma_intr (int irq, void *dev_instance,
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struct pt_regs *regs);
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static int adma_port_start(struct ata_port *ap);
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static void adma_host_stop(struct ata_host_set *host_set);
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static void adma_port_stop(struct ata_port *ap);
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static void adma_phy_reset(struct ata_port *ap);
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static void adma_qc_prep(struct ata_queued_cmd *qc);
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static int adma_qc_issue(struct ata_queued_cmd *qc);
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static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
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static void adma_bmdma_stop(struct ata_queued_cmd *qc);
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static u8 adma_bmdma_status(struct ata_port *ap);
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static void adma_irq_clear(struct ata_port *ap);
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static void adma_eng_timeout(struct ata_port *ap);
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static Scsi_Host_Template adma_ata_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ENABLE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ADMA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations adma_ata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.check_atapi_dma = adma_check_atapi_dma,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = adma_phy_reset,
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.qc_prep = adma_qc_prep,
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.qc_issue = adma_qc_issue,
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.eng_timeout = adma_eng_timeout,
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.irq_handler = adma_intr,
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.irq_clear = adma_irq_clear,
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.port_start = adma_port_start,
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.port_stop = adma_port_stop,
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.host_stop = adma_host_stop,
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.bmdma_stop = adma_bmdma_stop,
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.bmdma_status = adma_bmdma_status,
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};
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static struct ata_port_info adma_port_info[] = {
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/* board_1841_idx */
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{
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.sht = &adma_ata_sht,
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.host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
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ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO,
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.pio_mask = 0x10, /* pio4 */
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.udma_mask = 0x1f, /* udma0-4 */
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.port_ops = &adma_ata_ops,
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},
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};
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static struct pci_device_id adma_ata_pci_tbl[] = {
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{ PCI_VENDOR_ID_PDC, 0x1841, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_1841_idx },
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{ } /* terminate list */
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};
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static struct pci_driver adma_ata_pci_driver = {
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.name = DRV_NAME,
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.id_table = adma_ata_pci_tbl,
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.probe = adma_ata_init_one,
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.remove = ata_pci_remove_one,
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};
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static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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return 1; /* ATAPI DMA not yet supported */
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}
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static void adma_bmdma_stop(struct ata_queued_cmd *qc)
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{
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/* nothing */
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}
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static u8 adma_bmdma_status(struct ata_port *ap)
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{
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return 0;
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}
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static void adma_irq_clear(struct ata_port *ap)
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{
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/* nothing */
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}
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static void adma_reset_engine(void __iomem *chan)
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{
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/* reset ADMA to idle state */
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writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
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udelay(2);
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writew(aPIOMD4, chan + ADMA_CONTROL);
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udelay(2);
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}
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static void adma_reinit_engine(struct ata_port *ap)
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{
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struct adma_port_priv *pp = ap->private_data;
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void __iomem *mmio_base = ap->host_set->mmio_base;
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void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no);
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/* mask/clear ATA interrupts */
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writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr);
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ata_check_status(ap);
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/* reset the ADMA engine */
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adma_reset_engine(chan);
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/* set in-FIFO threshold to 0x100 */
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writew(0x100, chan + ADMA_FIFO_IN);
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/* set CPB pointer */
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writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
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/* set out-FIFO threshold to 0x100 */
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writew(0x100, chan + ADMA_FIFO_OUT);
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/* set CPB count */
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writew(1, chan + ADMA_CPB_COUNT);
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/* read/discard ADMA status */
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readb(chan + ADMA_STATUS);
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}
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static inline void adma_enter_reg_mode(struct ata_port *ap)
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{
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void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
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writew(aPIOMD4, chan + ADMA_CONTROL);
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readb(chan + ADMA_STATUS); /* flush */
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}
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static void adma_phy_reset(struct ata_port *ap)
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{
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struct adma_port_priv *pp = ap->private_data;
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pp->state = adma_state_idle;
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adma_reinit_engine(ap);
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ata_port_probe(ap);
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ata_bus_reset(ap);
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}
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static void adma_eng_timeout(struct ata_port *ap)
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{
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struct adma_port_priv *pp = ap->private_data;
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if (pp->state != adma_state_idle) /* healthy paranoia */
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pp->state = adma_state_mmio;
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adma_reinit_engine(ap);
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ata_eng_timeout(ap);
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}
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static int adma_fill_sg(struct ata_queued_cmd *qc)
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{
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struct scatterlist *sg = qc->sg;
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struct ata_port *ap = qc->ap;
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struct adma_port_priv *pp = ap->private_data;
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u8 *buf = pp->pkt;
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int nelem, i = (2 + buf[3]) * 8;
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u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
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for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
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u32 addr;
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u32 len;
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addr = (u32)sg_dma_address(sg);
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*(__le32 *)(buf + i) = cpu_to_le32(addr);
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i += 4;
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len = sg_dma_len(sg) >> 3;
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*(__le32 *)(buf + i) = cpu_to_le32(len);
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i += 4;
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if ((nelem + 1) == qc->n_elem)
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pFLAGS |= pEND;
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buf[i++] = pFLAGS;
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buf[i++] = qc->dev->dma_mode & 0xf;
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buf[i++] = 0; /* pPKLW */
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buf[i++] = 0; /* reserved */
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*(__le32 *)(buf + i)
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= (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
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i += 4;
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VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", nelem,
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(unsigned long)addr, len);
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}
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return i;
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}
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static void adma_qc_prep(struct ata_queued_cmd *qc)
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{
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struct adma_port_priv *pp = qc->ap->private_data;
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u8 *buf = pp->pkt;
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u32 pkt_dma = (u32)pp->pkt_dma;
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int i = 0;
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VPRINTK("ENTER\n");
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adma_enter_reg_mode(qc->ap);
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if (qc->tf.protocol != ATA_PROT_DMA) {
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ata_qc_prep(qc);
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return;
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}
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buf[i++] = 0; /* Response flags */
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buf[i++] = 0; /* reserved */
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buf[i++] = cVLD | cDAT | cIEN;
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i++; /* cLEN, gets filled in below */
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*(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
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i += 4; /* cNCPB */
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i += 4; /* cPRD, gets filled in below */
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buf[i++] = 0; /* reserved */
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buf[i++] = 0; /* reserved */
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buf[i++] = 0; /* reserved */
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buf[i++] = 0; /* reserved */
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/* ATA registers; must be a multiple of 4 */
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buf[i++] = qc->tf.device;
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buf[i++] = ADMA_REGS_DEVICE;
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if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
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buf[i++] = qc->tf.hob_nsect;
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buf[i++] = ADMA_REGS_SECTOR_COUNT;
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buf[i++] = qc->tf.hob_lbal;
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buf[i++] = ADMA_REGS_LBA_LOW;
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buf[i++] = qc->tf.hob_lbam;
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buf[i++] = ADMA_REGS_LBA_MID;
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buf[i++] = qc->tf.hob_lbah;
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buf[i++] = ADMA_REGS_LBA_HIGH;
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}
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buf[i++] = qc->tf.nsect;
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buf[i++] = ADMA_REGS_SECTOR_COUNT;
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buf[i++] = qc->tf.lbal;
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buf[i++] = ADMA_REGS_LBA_LOW;
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buf[i++] = qc->tf.lbam;
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buf[i++] = ADMA_REGS_LBA_MID;
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buf[i++] = qc->tf.lbah;
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buf[i++] = ADMA_REGS_LBA_HIGH;
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buf[i++] = 0;
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buf[i++] = ADMA_REGS_CONTROL;
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buf[i++] = rIGN;
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buf[i++] = 0;
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buf[i++] = qc->tf.command;
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buf[i++] = ADMA_REGS_COMMAND | rEND;
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buf[3] = (i >> 3) - 2; /* cLEN */
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*(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
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i = adma_fill_sg(qc);
|
||||
wmb(); /* flush PRDs and pkt to memory */
|
||||
#if 0
|
||||
/* dump out CPB + PRDs for debug */
|
||||
{
|
||||
int j, len = 0;
|
||||
static char obuf[2048];
|
||||
for (j = 0; j < i; ++j) {
|
||||
len += sprintf(obuf+len, "%02x ", buf[j]);
|
||||
if ((j & 7) == 7) {
|
||||
printk("%s\n", obuf);
|
||||
len = 0;
|
||||
}
|
||||
}
|
||||
if (len)
|
||||
printk("%s\n", obuf);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void adma_packet_start(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
|
||||
|
||||
VPRINTK("ENTER, ap %p\n", ap);
|
||||
|
||||
/* fire up the ADMA engine */
|
||||
writew(aPIOMD4 | aGO | aAUTEN, chan + ADMA_CONTROL);
|
||||
}
|
||||
|
||||
static int adma_qc_issue(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct adma_port_priv *pp = qc->ap->private_data;
|
||||
|
||||
switch (qc->tf.protocol) {
|
||||
case ATA_PROT_DMA:
|
||||
pp->state = adma_state_pkt;
|
||||
adma_packet_start(qc);
|
||||
return 0;
|
||||
|
||||
case ATA_PROT_ATAPI_DMA:
|
||||
BUG();
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
pp->state = adma_state_mmio;
|
||||
return ata_qc_issue_prot(qc);
|
||||
}
|
||||
|
||||
static inline unsigned int adma_intr_pkt(struct ata_host_set *host_set)
|
||||
{
|
||||
unsigned int handled = 0, port_no;
|
||||
u8 __iomem *mmio_base = host_set->mmio_base;
|
||||
|
||||
for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
|
||||
struct ata_port *ap = host_set->ports[port_no];
|
||||
struct adma_port_priv *pp;
|
||||
struct ata_queued_cmd *qc;
|
||||
void __iomem *chan = ADMA_REGS(mmio_base, port_no);
|
||||
u8 drv_stat, status = readb(chan + ADMA_STATUS);
|
||||
|
||||
if (status == 0)
|
||||
continue;
|
||||
handled = 1;
|
||||
adma_enter_reg_mode(ap);
|
||||
if ((ap->flags & ATA_FLAG_PORT_DISABLED))
|
||||
continue;
|
||||
pp = ap->private_data;
|
||||
if (!pp || pp->state != adma_state_pkt)
|
||||
continue;
|
||||
qc = ata_qc_from_tag(ap, ap->active_tag);
|
||||
drv_stat = 0;
|
||||
if ((status & (aPERR | aPSD | aUIRQ)))
|
||||
drv_stat = ATA_ERR;
|
||||
else if (pp->pkt[0] != cDONE)
|
||||
drv_stat = ATA_ERR;
|
||||
ata_qc_complete(qc, drv_stat);
|
||||
}
|
||||
return handled;
|
||||
}
|
||||
|
||||
static inline unsigned int adma_intr_mmio(struct ata_host_set *host_set)
|
||||
{
|
||||
unsigned int handled = 0, port_no;
|
||||
|
||||
for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
|
||||
struct ata_port *ap;
|
||||
ap = host_set->ports[port_no];
|
||||
if (ap && (!(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))) {
|
||||
struct ata_queued_cmd *qc;
|
||||
struct adma_port_priv *pp = ap->private_data;
|
||||
if (!pp || pp->state != adma_state_mmio)
|
||||
continue;
|
||||
qc = ata_qc_from_tag(ap, ap->active_tag);
|
||||
if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
|
||||
|
||||
/* check main status, clearing INTRQ */
|
||||
u8 status = ata_chk_status(ap);
|
||||
if ((status & ATA_BUSY))
|
||||
continue;
|
||||
DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
|
||||
ap->id, qc->tf.protocol, status);
|
||||
|
||||
/* complete taskfile transaction */
|
||||
pp->state = adma_state_idle;
|
||||
ata_qc_complete(qc, status);
|
||||
handled = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
return handled;
|
||||
}
|
||||
|
||||
static irqreturn_t adma_intr(int irq, void *dev_instance, struct pt_regs *regs)
|
||||
{
|
||||
struct ata_host_set *host_set = dev_instance;
|
||||
unsigned int handled = 0;
|
||||
|
||||
VPRINTK("ENTER\n");
|
||||
|
||||
spin_lock(&host_set->lock);
|
||||
handled = adma_intr_pkt(host_set) | adma_intr_mmio(host_set);
|
||||
spin_unlock(&host_set->lock);
|
||||
|
||||
VPRINTK("EXIT\n");
|
||||
|
||||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
|
||||
static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base)
|
||||
{
|
||||
port->cmd_addr =
|
||||
port->data_addr = base + 0x000;
|
||||
port->error_addr =
|
||||
port->feature_addr = base + 0x004;
|
||||
port->nsect_addr = base + 0x008;
|
||||
port->lbal_addr = base + 0x00c;
|
||||
port->lbam_addr = base + 0x010;
|
||||
port->lbah_addr = base + 0x014;
|
||||
port->device_addr = base + 0x018;
|
||||
port->status_addr =
|
||||
port->command_addr = base + 0x01c;
|
||||
port->altstatus_addr =
|
||||
port->ctl_addr = base + 0x038;
|
||||
}
|
||||
|
||||
static int adma_port_start(struct ata_port *ap)
|
||||
{
|
||||
struct device *dev = ap->host_set->dev;
|
||||
struct adma_port_priv *pp;
|
||||
int rc;
|
||||
|
||||
rc = ata_port_start(ap);
|
||||
if (rc)
|
||||
return rc;
|
||||
adma_enter_reg_mode(ap);
|
||||
rc = -ENOMEM;
|
||||
pp = kcalloc(1, sizeof(*pp), GFP_KERNEL);
|
||||
if (!pp)
|
||||
goto err_out;
|
||||
pp->pkt = dma_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
|
||||
GFP_KERNEL);
|
||||
if (!pp->pkt)
|
||||
goto err_out_kfree;
|
||||
/* paranoia? */
|
||||
if ((pp->pkt_dma & 7) != 0) {
|
||||
printk("bad alignment for pp->pkt_dma: %08x\n",
|
||||
(u32)pp->pkt_dma);
|
||||
goto err_out_kfree2;
|
||||
}
|
||||
memset(pp->pkt, 0, ADMA_PKT_BYTES);
|
||||
ap->private_data = pp;
|
||||
adma_reinit_engine(ap);
|
||||
return 0;
|
||||
|
||||
err_out_kfree2:
|
||||
kfree(pp);
|
||||
err_out_kfree:
|
||||
kfree(pp);
|
||||
err_out:
|
||||
ata_port_stop(ap);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void adma_port_stop(struct ata_port *ap)
|
||||
{
|
||||
struct device *dev = ap->host_set->dev;
|
||||
struct adma_port_priv *pp = ap->private_data;
|
||||
|
||||
adma_reset_engine(ADMA_REGS(ap->host_set->mmio_base, ap->port_no));
|
||||
if (pp != NULL) {
|
||||
ap->private_data = NULL;
|
||||
if (pp->pkt != NULL)
|
||||
dma_free_coherent(dev, ADMA_PKT_BYTES,
|
||||
pp->pkt, pp->pkt_dma);
|
||||
kfree(pp);
|
||||
}
|
||||
ata_port_stop(ap);
|
||||
}
|
||||
|
||||
static void adma_host_stop(struct ata_host_set *host_set)
|
||||
{
|
||||
unsigned int port_no;
|
||||
|
||||
for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
|
||||
adma_reset_engine(ADMA_REGS(host_set->mmio_base, port_no));
|
||||
|
||||
ata_pci_host_stop(host_set);
|
||||
}
|
||||
|
||||
static void adma_host_init(unsigned int chip_id,
|
||||
struct ata_probe_ent *probe_ent)
|
||||
{
|
||||
unsigned int port_no;
|
||||
void __iomem *mmio_base = probe_ent->mmio_base;
|
||||
|
||||
/* enable/lock aGO operation */
|
||||
writeb(7, mmio_base + ADMA_MODE_LOCK);
|
||||
|
||||
/* reset the ADMA logic */
|
||||
for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
|
||||
adma_reset_engine(ADMA_REGS(mmio_base, port_no));
|
||||
}
|
||||
|
||||
static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
if (rc) {
|
||||
printk(KERN_ERR DRV_NAME
|
||||
"(%s): 32-bit DMA enable failed\n",
|
||||
pci_name(pdev));
|
||||
return rc;
|
||||
}
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
if (rc) {
|
||||
printk(KERN_ERR DRV_NAME
|
||||
"(%s): 32-bit consistent DMA enable failed\n",
|
||||
pci_name(pdev));
|
||||
return rc;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int adma_ata_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
struct ata_probe_ent *probe_ent = NULL;
|
||||
void __iomem *mmio_base;
|
||||
unsigned int board_idx = (unsigned int) ent->driver_data;
|
||||
int rc, port_no;
|
||||
|
||||
if (!printed_version++)
|
||||
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
|
||||
|
||||
rc = pci_enable_device(pdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = pci_request_regions(pdev, DRV_NAME);
|
||||
if (rc)
|
||||
goto err_out;
|
||||
|
||||
if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
|
||||
rc = -ENODEV;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
mmio_base = pci_iomap(pdev, 4, 0);
|
||||
if (mmio_base == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
rc = adma_set_dma_masks(pdev, mmio_base);
|
||||
if (rc)
|
||||
goto err_out_iounmap;
|
||||
|
||||
probe_ent = kcalloc(1, sizeof(*probe_ent), GFP_KERNEL);
|
||||
if (probe_ent == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_iounmap;
|
||||
}
|
||||
|
||||
probe_ent->dev = pci_dev_to_dev(pdev);
|
||||
INIT_LIST_HEAD(&probe_ent->node);
|
||||
|
||||
probe_ent->sht = adma_port_info[board_idx].sht;
|
||||
probe_ent->host_flags = adma_port_info[board_idx].host_flags;
|
||||
probe_ent->pio_mask = adma_port_info[board_idx].pio_mask;
|
||||
probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask;
|
||||
probe_ent->udma_mask = adma_port_info[board_idx].udma_mask;
|
||||
probe_ent->port_ops = adma_port_info[board_idx].port_ops;
|
||||
|
||||
probe_ent->irq = pdev->irq;
|
||||
probe_ent->irq_flags = SA_SHIRQ;
|
||||
probe_ent->mmio_base = mmio_base;
|
||||
probe_ent->n_ports = ADMA_PORTS;
|
||||
|
||||
for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
|
||||
adma_ata_setup_port(&probe_ent->port[port_no],
|
||||
ADMA_ATA_REGS((unsigned long)mmio_base, port_no));
|
||||
}
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
/* initialize adapter */
|
||||
adma_host_init(board_idx, probe_ent);
|
||||
|
||||
rc = ata_device_add(probe_ent);
|
||||
kfree(probe_ent);
|
||||
if (rc != ADMA_PORTS)
|
||||
goto err_out_iounmap;
|
||||
return 0;
|
||||
|
||||
err_out_iounmap:
|
||||
pci_iounmap(pdev, mmio_base);
|
||||
err_out_regions:
|
||||
pci_release_regions(pdev);
|
||||
err_out:
|
||||
pci_disable_device(pdev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __init adma_ata_init(void)
|
||||
{
|
||||
return pci_module_init(&adma_ata_pci_driver);
|
||||
}
|
||||
|
||||
static void __exit adma_ata_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&adma_ata_pci_driver);
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Mark Lord");
|
||||
MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
|
||||
module_init(adma_ata_init);
|
||||
module_exit(adma_ata_exit);
|
||||
Loading…
Reference in New Issue
Block a user