dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock
The PRG_ETHERNET registers can add an RX delay in RGMII mode. This requires an internal re-timing circuit whose input clock is called "timing adjustment clock". Document this clock input so the clock can be enabled as needed. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -40,18 +40,22 @@ allOf:
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 4
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items:
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- description: GMAC main clock
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- description: First parent clock of the internal mux
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- description: Second parent clock of the internal mux
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- description: The clock which drives the timing adjustment logic
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clock-names:
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minItems: 3
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maxItems: 3
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maxItems: 4
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items:
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- const: stmmaceth
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- const: clkin0
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- const: clkin1
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- const: timing-adjustment
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amlogic,tx-delay-ns:
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$ref: /schemas/types.yaml#definitions/uint32
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@ -120,7 +124,7 @@ examples:
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reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
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interrupts = <8>;
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interrupt-names = "macirq";
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clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
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clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
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phy-mode = "rgmii";
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};
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