From 8e57eed2047b9361deb8c5dc4cc3d4e679c5ce50 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:47 +0200 Subject: [PATCH 01/20] arm64: dts: rockchip: fix iface clock-name on px30 iommus The iommu clock names are aclk+iface not aclk+hclk as in the vendor kernel, so fix that in the px30.dtsi Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-1-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index eb992d60e6ba..1fd12bd09e83 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -831,7 +831,7 @@ interrupts = ; interrupt-names = "vopb_mmu"; clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; - clock-names = "aclk", "hclk"; + clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; #iommu-cells = <0>; status = "disabled"; @@ -863,7 +863,7 @@ interrupts = ; interrupt-names = "vopl_mmu"; clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; - clock-names = "aclk", "hclk"; + clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; #iommu-cells = <0>; status = "disabled"; From 00519137f7d4fc19ff27f3d3f4fc45b5b222ae82 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:48 +0200 Subject: [PATCH 02/20] arm64: dts: rockchip: remove static xin32k from px30 Similar to all other Rockchip SoCs the px30 does not have a static 32kHz clock. Instead it again gets supplied from an external component like the pmic. So drop the static clock, so that we can hook up the right one. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-2-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 1fd12bd09e83..06328f1b05e8 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -195,13 +195,6 @@ clock-output-names = "xin24m"; }; - xin32k: xin32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; - pmu: power-management@ff000000 { compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff000000 0x0 0x1000>; From f77ccf399e3b5d9adeed6bff43f684f7200cbb0c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:49 +0200 Subject: [PATCH 03/20] arm64: dts: rockchip: remove px30 emmc_pwren pinctrl That gpio1-b0 can only be flash_cs apart from a regular gpio, so there is no power-related pinmux for the emmc for this pin. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-3-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 06328f1b05e8..a178d6e2c279 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1648,11 +1648,6 @@ <1 RK_PB2 2 &pcfg_pull_up_8ma>; }; - emmc_pwren: emmc-pwren { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_none>; - }; - emmc_rstnout: emmc-rstnout { rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; From cdfebb27892a66580d770f6c57f3deb5024b4d08 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:50 +0200 Subject: [PATCH 04/20] arm64: dts: rockchip: add default px30 emmc pinctrl emmc chips are normally hooked up in standard ways using the full 8bit bus connection, so there should be no need for all future boards to define this on their own. So add default pin setups for 8bit busses and special boards really only needing 4 or 1 bit connections can override. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-4-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index a178d6e2c279..f2bbdfa0e4aa 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -794,6 +794,8 @@ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; power-domains = <&power PX30_PD_MMC_NAND>; status = "disabled"; }; From 915b6a8b54a6d436885a458867e59fb20fc6356d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:51 +0200 Subject: [PATCH 05/20] arm64: dts: rockchip: fix the px30-evb power tree Add the board's pmic (rk809) and hook up the real supplies to their consumers. This is especially important as cpufreq would otherwise hang the system when scaling the frequency without adjusting the voltage. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-5-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 254 +++++++++++++++++++++- 1 file changed, 246 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 6eb7407a84aa..d78fb172a66f 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -58,6 +58,7 @@ backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 25000 0>; + power-supply = <&vcc3v3_lcd>; }; sdio_pwrseq: sdio-pwrseq { @@ -74,13 +75,6 @@ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ }; - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - vcc5v0_sys: vccsys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -91,6 +85,22 @@ }; }; +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + &display_subsystem { status = "okay"; }; @@ -100,12 +110,14 @@ cap-mmc-highspeed; mmc-hs200-1_8v; non-removable; + vmmc-supply = <&vcc_3v0>; + vqmmc-supply = <&vccio_flash>; status = "okay"; }; &gmac { clock_in_out = "output"; - phy-supply = <&vcc_phy>; + phy-supply = <&vcc_rmii>; snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 50000 50000>; @@ -114,6 +126,219 @@ &i2c0 { status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0>; + clock-output-names = "xin32k"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: vcc_rmii: DCDC_REG4 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-name = "vcc2v8_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v5_dvp: LDO_REG9 { + regulator-name = "vcc1v5_dvp"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; &i2s1_2ch { @@ -122,6 +347,13 @@ &io_domains { status = "okay"; + + vccio1-supply = <&vccio_sdio>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + vccio6-supply = <&vccio_flash>; }; &pinctrl { @@ -164,6 +396,9 @@ &pmu_io_domains { status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; }; &pwm1 { @@ -171,6 +406,7 @@ }; &saradc { + vref-supply = <&vcc_1v8>; status = "okay"; }; @@ -183,6 +419,8 @@ sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; status = "okay"; }; From 79fd8ba2fd2c64858253796abc2d9cc6c26d1e6d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:52 +0200 Subject: [PATCH 06/20] arm64: dts: rockchip: add emmc-powersequence to px30-evb Hook the reset line into an emmc-pwrseq for it to get initialized nicely. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-6-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index d78fb172a66f..6d50f6abcb48 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -61,6 +61,13 @@ power-supply = <&vcc3v3_lcd>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -110,6 +117,7 @@ cap-mmc-highspeed; mmc-hs200-1_8v; non-removable; + mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v0>; vqmmc-supply = <&vccio_flash>; status = "okay"; @@ -364,6 +372,12 @@ }; }; + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = From 9003aacb9cc3496947534b57f95913b147a9102c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:53 +0200 Subject: [PATCH 07/20] arm64: dts: rockchip: move px30-evb console output to uart 5 The px30-evb exposes uart2 through a uart-to-usb converter on the board but these pins are shared with the sdmmc controller. With both activated this results in a race condition depending in the probe order. Whichever of the two probes first will break the other peripheral. The px30-evb also exposes uart5 through pin its pin headers, so it's way saner to use these pins for serial output and keep the sdmmc working in all cases. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-7-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 6d50f6abcb48..80524afe94da 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -14,7 +14,7 @@ compatible = "rockchip,px30-evb", "rockchip,px30"; chosen { - stdout-path = "serial2:1500000n8"; + stdout-path = "serial5:115200n8"; }; adc-keys { @@ -454,7 +454,7 @@ status = "okay"; }; -&uart2 { +&uart5 { status = "okay"; }; From 689c7dc73c26834bc70aa06065ff44df991cd975 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:54 +0200 Subject: [PATCH 08/20] arm64: dts: rockchip: remove unused pin settings from px30 These are unused gpio-settings for specific function pins, that are not used by anything and only clutter up the dtsi. They can be re-added when a relevant user is added. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-8-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30.dtsi | 40 -------------------------- 1 file changed, 40 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index f2bbdfa0e4aa..63499d27994c 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1159,11 +1159,6 @@ rockchip,pins = <0 RK_PB5 1 &pcfg_pull_none>; }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = - <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; }; uart1 { @@ -1182,11 +1177,6 @@ rockchip,pins = <1 RK_PC3 1 &pcfg_pull_none>; }; - - uart1_rts_gpio: uart1-rts-gpio { - rockchip,pins = - <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; }; uart2-m0 { @@ -1221,11 +1211,6 @@ rockchip,pins = <0 RK_PC3 2 &pcfg_pull_none>; }; - - uart3m0_rts_gpio: uart3m0-rts-gpio { - rockchip,pins = - <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; }; uart3-m1 { @@ -1244,11 +1229,6 @@ rockchip,pins = <1 RK_PB5 2 &pcfg_pull_none>; }; - - uart3m1_rts_gpio: uart3m1-rts-gpio { - rockchip,pins = - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; }; uart4 { @@ -1597,16 +1577,6 @@ <1 RK_PD4 1 &pcfg_pull_up_8ma>, <1 RK_PD5 1 &pcfg_pull_up_8ma>; }; - - sdmmc_gpio: sdmmc-gpio { - rockchip,pins = - <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; }; sdio { @@ -1627,16 +1597,6 @@ <1 RK_PD0 1 &pcfg_pull_up>, <1 RK_PD1 1 &pcfg_pull_up>; }; - - sdio_gpio: sdio-gpio { - rockchip,pins = - <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; }; emmc { From 45cb61b4f3bf991ac2011dbc4a155bd5f3b29ebe Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:55 +0200 Subject: [PATCH 09/20] arm64: dts: rockchip: document explicit px30 cru dependencies The px30 contains 2 separate clock controllers the regular cru creating most clocks as well as the pmucru managing the GPLL and some other clocks. The gpll of course also is needed by the cru, so while we normally do rely on clock names to associate clocks getting probed later on (for example xin32k coming from an i2c device in most cases) it is safer to declare the explicit dependency between the two crus. This makes sure that for example the clock-framework probes them in the correct order from the start. The assigned-clocks properties were simply working by chance in the past so split them accordingly to the 2 crus to honor the loading direction. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20190917082659.25549-9-heiko@sntech.de --- .../bindings/clock/rockchip,px30-cru.txt | 5 ++++ arch/arm64/boot/dts/rockchip/px30.dtsi | 25 +++++++++++-------- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt index 39f0c1ac84ee..55e78cddec8c 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt @@ -10,6 +10,11 @@ Required Properties: - compatible: CRU should be "rockchip,px30-cru" - reg: physical base address of the controller and length of memory mapped region. +- clocks: A list of phandle + clock-specifier pairs for the clocks listed + in clock-names +- clock-names: Should contain the following: + - "xin24m" for both PMUCRU and CRU + - "gpll" for CRU (sourced from PMUCRU) - #clock-cells: should be 1. - #reset-cells: should be 1. diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 63499d27994c..9ad1c2f04ea9 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -667,33 +667,38 @@ cru: clock-controller@ff2b0000 { compatible = "rockchip,px30-cru"; reg = <0x0 0xff2b0000 0x0 0x1000>; + clocks = <&xin24m>, <&pmucru PLL_GPLL>; + clock-names = "xin24m", "gpll"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_NPLL>; - assigned-clock-rates = <1188000000>; + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; }; pmucru: clock-controller@ff2bc000 { compatible = "rockchip,px30-pmucru"; reg = <0x0 0xff2bc000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; + <&pmucru SCLK_WIFI_PMU>; assigned-clock-rates = <1200000000>, <100000000>, - <26000000>, <600000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>; + <26000000>; }; usb20_otg: usb@ff300000 { From 52462ac6277fa30ba3829975d0745fd0b740e433 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:56 +0200 Subject: [PATCH 10/20] arm64: dts: rockchip: add px30-evb i2c1 devices Enable i2c1 and adds the devices connected to it. This includes a magnetometer, goodix-touchscreen and accelerometer. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917082659.25549-10-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 80524afe94da..1185a314ba4a 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -349,6 +349,43 @@ }; }; +&i2c1 { + status = "okay"; + + sensor@d { + compatible = "asahi-kasei,ak8963"; + reg = <0x0d>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&vcc3v0_pmu>; + mount-matrix = "1", /* x0 */ + "0", /* y0 */ + "0", /* z0 */ + "0", /* x1 */ + "1", /* y1 */ + "0", /* z1 */ + "0", /* x2 */ + "0", /* y2 */ + "1"; /* z2 */ + }; + + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vcc3v3_lcd>; + }; + + sensor@4c { + compatible = "fsl,mma7660"; + reg = <0x4c>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + &i2s1_2ch { status = "okay"; }; From c595826faa9705e04ef6ec4de2b1c6775815482b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:57 +0200 Subject: [PATCH 11/20] dt-bindings: document PX30 usb2phy General Register Files One of the separate General Register Files contains the registers for controlling the usb2phy, so add the necessary binding compatible for it. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring Link: https://lore.kernel.org/r/20190917082659.25549-11-heiko@sntech.de --- Documentation/devicetree/bindings/soc/rockchip/grf.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index 46e27cd69f18..d7debec26ba4 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -30,6 +30,7 @@ Required Properties: - compatible: SGRF should be one of the following - "rockchip,rk3288-sgrf", "syscon": for rk3288 - compatible: USB2PHYGRF should be one of the followings + - "rockchip,px30-usb2phy-grf", "syscon": for px30 - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 - compatible: USBGRF should be one of the following - "rockchip,rv1108-usbgrf", "syscon": for rv1108 From f1b3b7077b40b4890c5efed82f5b06854fed4811 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 19 Sep 2019 10:58:21 +0530 Subject: [PATCH 12/20] arm64: dts: rockchip: Rename vcc12v_sys into dc_12v for roc-rk3399-pc It is always better practice to follow regulator naming conventions as per the schematics for future references. This would indeed helpful to review and check the naming convention directly on schematics, both for the code reviewers and the developers. So, rename vcc12v_sys into dc_12v as per rk3399 power tree as per roc-rk3399-pc schematics. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20190919052822.10403-6-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts index 19f7732d728c..603c4d7274b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts @@ -57,9 +57,9 @@ * should be placed inside mp8859, but not until mp8859 has * its own dt-binding. */ - vcc12v_sys: mp8859-dcdc1 { + dc_12v: mp8859-dcdc1 { compatible = "regulator-fixed"; - regulator-name = "vcc12v_sys"; + regulator-name = "dc_12v"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <12000000>; @@ -85,7 +85,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_sys>; + vin-supply = <&dc_12v>; }; /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ @@ -118,7 +118,7 @@ regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_sys>; + vin-supply = <&dc_12v>; }; vdd_log: vdd-log { From 9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 19 Sep 2019 10:58:22 +0530 Subject: [PATCH 13/20] arm64: dts: rockchip: Fix roc-rk3399-pc regulator input rails Few, know rk808 pmic regulators VCC[1-4], VCC[6-7], VCC[9-11], VDD_LOG, VDD_GPU, VDD_CPU_B, VCC3V3_SYS are inputting with vcc_sys which is 5V power rail from dc_12v. So, replace the vin-supply of above mentioned regulators with vcc_sys as per the PMIC-RK808-D page of roc-rk3399-pc schematics. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20190919052822.10403-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3399-roc-pc.dts | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts index 603c4d7274b8..257543d069d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts @@ -85,7 +85,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&vcc_sys>; }; /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ @@ -129,7 +129,7 @@ regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc3v3_sys>; + vin-supply = <&vcc_sys>; }; }; @@ -202,16 +202,16 @@ rockchip,system-power-controller; wakeup-source; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc3v3_sys>; vddio-supply = <&vcc1v8_pmu>; @@ -385,7 +385,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc3v3_sys>; + vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -404,7 +404,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc3v3_sys>; + vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; From 85dd7638505823f38d491ab6b4e52b3ab9349149 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:36:25 +0200 Subject: [PATCH 14/20] arm64: dts: rockchip: add missing #msi-cells to rk3399 The rk3399 gic-its was missing the #msi-cells property as found by dt-schema checks, so add it. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20190917083625.25818-1-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cede1ad81be2..e62ea0e2b657 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -520,6 +520,7 @@ its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xfee20000 0x0 0x20000>; }; From 6860769ea771cf7fdb77c0f1333096c9700be141 Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Sun, 8 Sep 2019 02:48:33 +0900 Subject: [PATCH 15/20] arm64: dts: rockchip: add analog audio nodes on rk3399-rockpro64 This patch adds audio codec (Everest ES8316) and I2S audio nodes for RK3399 RockPro64. Signed-off-by: Katsuhiro Suzuki Link: https://lore.kernel.org/r/20190907174833.19957-1-katsuhiro@katsuster.net Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rockpro64.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 0401d4ec1f45..8b1e6382b140 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -81,6 +81,12 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3399"; + dais = <&i2s1_p0>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -470,6 +476,20 @@ i2c-scl-rising-time-ns = <300>; i2c-scl-falling-time-ns = <15>; status = "okay"; + + es8316: codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; + }; }; &i2c3 { @@ -505,6 +525,14 @@ rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; }; &i2s2 { From 87d8ae980e1944331f93e0488e16bd3bec4554c7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 22 Aug 2018 14:09:25 +0200 Subject: [PATCH 16/20] arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bob Scarlet and Bob use the Google-developed cr50 chip to do things like TPM and closed-case-debugging. Add the nodes describing the cr50 and its spi-connection. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20180822120925.12388-1-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts index a9f4d6d7d2b7..9dd3b171e91d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -68,6 +68,16 @@ &spi0 { status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + spi-max-frequency = <800000>; + }; }; &pinctrl { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 50dfab51f175..4373ed732af7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -436,6 +436,16 @@ camera: &i2c7 { &spi2 { status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + spi-max-frequency = <800000>; + }; }; &usb_host0_ohci { From f94ffd95cb7699ec424e856d42f03b12d67f71a4 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 7 Oct 2019 12:33:25 +0100 Subject: [PATCH 17/20] arm64: dts: rockchip: Enable nanopi4 HDMI audio All the nanopi4 boards have HDMI, so let them make noise on it. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/7fe6e94e4b9f5986f19f2637b7b716f0cb54de1b.1570444701.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index dd16c80d923e..3bd4cbf9cf4a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -184,6 +184,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <160>; @@ -459,6 +463,10 @@ status = "okay"; }; +&i2s2 { + status = "okay"; +}; + &io_domains { bt656-supply = <&vcc_1v8>; audio-supply = <&vcca1v8_codec>; From bc43cee88aa128c32239a87c523af7c531589f6d Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 7 Oct 2019 12:33:26 +0100 Subject: [PATCH 18/20] arm64: dts: rockchip: Update nanopi4 phy reset properties Use the now-preferred generic phy reset properties instead of the dwmac-specific ones. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/4d16c24ae3651a2119cf5bb1213f46a9fce4b39a.1570444773.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 3bd4cbf9cf4a..b788ae4f47f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -152,9 +152,6 @@ phy-handle = <&rtl8211e>; phy-mode = "rgmii"; phy-supply = <&vcc3v3_s3>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; tx_delay = <0x28>; rx_delay = <0x11>; status = "okay"; @@ -168,6 +165,9 @@ reg = <1>; interrupt-parent = <&gpio3>; interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; }; }; }; From 4ff75253719cfae945ffb7d0f91293b236d7c717 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 15 Oct 2019 22:58:51 +0200 Subject: [PATCH 19/20] arm64: dts: rockchip: restyle rockchip,pins on rk3399-rock-pi-4 The define RK_FUNC_1 is no longer used, so restyle the rockchip,pins definitions. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20191015205852.4200-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rock-pi-4.dts | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts index 1ae1ebd4efdd..188d9dfc297b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts @@ -486,21 +486,18 @@ sdio0 { sdio0_bus4: sdio0-bus4 { - rockchip,pins = - <2 20 RK_FUNC_1 &pcfg_pull_up_20ma>, - <2 21 RK_FUNC_1 &pcfg_pull_up_20ma>, - <2 22 RK_FUNC_1 &pcfg_pull_up_20ma>, - <2 23 RK_FUNC_1 &pcfg_pull_up_20ma>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; }; sdio0_cmd: sdio0-cmd { - rockchip,pins = - <2 24 RK_FUNC_1 &pcfg_pull_up_20ma>; + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; }; sdio0_clk: sdio0-clk { - rockchip,pins = - <2 25 RK_FUNC_1 &pcfg_pull_none_20ma>; + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; }; }; @@ -532,8 +529,7 @@ wifi { wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; wifi_host_wake_l: wifi-host-wake-l { From d083ce427947bbf10358e4c12bf20f288ee6b3df Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 15 Oct 2019 22:58:52 +0200 Subject: [PATCH 20/20] include: dt-bindings: rockchip: mark RK_FUNC defines as deprecated The defines RK_FUNC_1, RK_FUNC_2, RK_FUNC_3 and RK_FUNC_4 are no longer used. Mark them as "deprecated" to prevent that someone start using them again. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20191015205852.4200-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- include/dt-bindings/pinctrl/rockchip.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index dc5c1c73d030..6d6bac1c26d7 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -50,9 +50,9 @@ #define RK_PD7 31 #define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 -#define RK_FUNC_2 2 -#define RK_FUNC_3 3 -#define RK_FUNC_4 4 +#define RK_FUNC_1 1 /* deprecated */ +#define RK_FUNC_2 2 /* deprecated */ +#define RK_FUNC_3 3 /* deprecated */ +#define RK_FUNC_4 4 /* deprecated */ #endif