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perf vendors events arm64: Arm Cortex-A34

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Add PMU events for Arm Cortex-A34
Add corresponding common events
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a34.json

which is based on PMU event descriptions from the Arm Cortex-A34 Technical
Reference Manual.

Common event data based on:
https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json

which is based on PMU event descriptions found in the Arm Architecture
Reference Manual:
https://developer.arm.com/documentation/ddi0487/

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Nick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220520181455.340344-2-nick.forrington@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Nick Forrington 2022-05-20 19:14:43 +01:00 committed by Arnaldo Carvalho de Melo
parent d8fc085509
commit ee2409510c
8 changed files with 148 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json Normal file
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@ -0,0 +1,11 @@
[
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
}
]

17
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json Normal file
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@ -0,0 +1,17 @@
[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
}
]

32
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json Normal file
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@ -0,0 +1,32 @@
[
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L1D_CACHE_WB"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
}
]

14
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json Normal file
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@ -0,0 +1,14 @@
[
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
}
]

29
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json Normal file
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@ -0,0 +1,29 @@
[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
}
]

8
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json Normal file
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@ -0,0 +1,8 @@
[
{
"ArchStdEvent": "UNALIGNED_LDST_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS"
}
]

36
tools/perf/pmu-events/arch/arm64/common-and-microarch.json
View File

@ -35,6 +35,18 @@
"EventName": "L1D_TLB_REFILL",
"BriefDescription": "Attributable Level 1 data TLB refill"
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, load",
"EventCode": "0x06",
"EventName": "LD_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, load"
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, store",
"EventCode": "0x07",
"EventName": "ST_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, store"
},
{
"PublicDescription": "Instruction architecturally executed",
"EventCode": "0x08",
@ -59,6 +71,30 @@
"EventName": "CID_WRITE_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR"
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, software change of the PC",
"EventCode": "0x0C",
"EventName": "PC_WRITE_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, software change of the PC"
},
{
"PublicDescription": "Instruction architecturally executed, immediate branch",
"EventCode": "0x0D",
"EventName": "BR_IMMED_RETIRED",
"BriefDescription": "Instruction architecturally executed, immediate branch"
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, procedure return",
"EventCode": "0x0E",
"EventName": "BR_RETURN_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, procedure return"
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, unaligned",
"EventCode": "0x0F",
"EventName": "UNALIGNED_LDST_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, unaligned"
},
{
"PublicDescription": "Mispredicted or not predicted branch speculatively executed",
"EventCode": "0x10",

1
tools/perf/pmu-events/arch/arm64/mapfile.csv
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@ -12,6 +12,7 @@
#
#
#Family-model,Version,Filename,EventType
0x00000000410fd020,v1,arm/cortex-a34,core
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
0x00000000410fd070,v1,arm/cortex-a57-a72,core

1 # Format:
12 #
13 #
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,core
18 0x00000000410fd070,v1,arm/cortex-a57-a72,core