dt-bindings: pinctrl: realtek: add RTD1315E pinctrl binding
Add device tree bindings for RTD1315E. Signed-off-by: Tzuyi Chang <tychang@realtek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230919101117.4097-6-tychang@realtek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Tzuyi Chang
Linus Walleij
parent
c7910f6aca
commit
ee3014e863
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2023 Realtek Semiconductor Corporation
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Realtek DHC RTD1315E Pin Controller
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maintainers:
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- TY Chang <tychang@realtek.com>
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description:
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The Realtek DHC RTD1315E is a high-definition media processor SoC. The
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RTD1315E pin controller is used to control pin function, pull up/down
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resistor, drive strength, schmitt trigger and power source.
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properties:
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compatible:
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const: realtek,rtd1315e-pinctrl
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reg:
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maxItems: 1
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patternProperties:
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'-pins$':
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type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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properties:
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pins:
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items:
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enum: [ gpio_0, gpio_1, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd,
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gpio_6, gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12,
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gpio_13, gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19,
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gpio_20, emmc_data_0, emmc_data_1, emmc_data_2, usb_cc2, gpio_25,
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gpio_26, gpio_27, gpio_28, gpio_29, gpio_30, gpio_31, gpio_32,
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gpio_33, gpio_34, gpio_35, hif_data, hif_en, hif_rdy, hif_clk,
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gpio_dummy_40, gpio_dummy_41, gpio_dummy_42, gpio_dummy_43,
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gpio_dummy_44, gpio_dummy_45, gpio_46, gpio_47, gpio_48, gpio_49,
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gpio_50, usb_cc1, emmc_data_3, emmc_data_4, ir_rx, ur0_rx, ur0_tx,
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gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_dummy_63,
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gpio_dummy_64, gpio_dummy_65, gpio_66, gpio_67, gpio_68, gpio_69,
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gpio_70, gpio_71, gpio_72, gpio_dummy_73, emmc_data_5, emmc_data_6,
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emmc_data_7, gpio_dummy_77, gpio_78, gpio_79, gpio_80, gpio_81,
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ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en,
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ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc,
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dmic_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc, tdm_ai_loc,
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ai_loc, spdif_loc, hif_en_loc, scan_switch, wd_rset, boot_sel,
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reset_n, testmode ]
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function:
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enum: [ gpio, nf, emmc, ao, gspi_loc0, gspi_loc1, uart0, uart1,
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uart2_loc0, uart2_loc1, i2c0, i2c1, i2c4, i2c5, pcie1,
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etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1, pwm1_loc0,
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pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1,
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spdif_optical_loc0, spdif_optical_loc1, usb_cc1, usb_cc2,
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sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1, tdm_ai_loc0,
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tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0,
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vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0,
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vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1,
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ir_rx, uart2_disable, gspi_disable, hi_width_disable,
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hi_width_1bit, sf_disable, sf_enable, scpu_ejtag_loc0,
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scpu_ejtag_loc1, scpu_ejtag_loc2, scpu_ejtag_loc3,
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acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2,
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vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2,
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aucpu_ejtag_loc0, aucpu_ejtag_loc1, aucpu_ejtag_loc2,
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gpu_ejtag, iso_tristate, dbg_out0, dbg_out1, standby_dbg,
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spdif, arm_trace_debug_disable, arm_trace_debug_enable,
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aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable,
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scpu_ejtag_disable, vtc_dmic_loc_disable, vtc_tdm_disable,
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vtc_i2si_disable, tdm_ai_disable, ai_disable, spdif_disable,
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hif_disable, hif_enable, test_loop, pmic_pwrup ]
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drive-strength:
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enum: [4, 8]
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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drive-push-pull: true
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power-source:
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description: |
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Valid arguments are described as below:
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0: power supply of 1.8V
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1: power supply of 3.3V
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enum: [0, 1]
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realtek,drive-strength-p:
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description: |
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Some of pins can be driven using the P-MOS and N-MOS transistor to
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achieve finer adjustments. The block-diagram representation is as
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follows:
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VDD
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||--+
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+-----o|| P-MOS-FET
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| ||--+
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IN --+ +----- out
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| ||--+
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+------|| N-MOS-FET
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||--+
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GND
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The driving strength of the P-MOS/N-MOS transistors impacts the
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waveform's rise/fall times. Greater driving strength results in
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shorter rise/fall times. Each P-MOS and N-MOS transistor offers
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8 configurable levels (0 to 7), with higher values indicating
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greater driving strength, contributing to achieving the desired
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speed.
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The realtek,drive-strength-p is used to control the driving strength
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of the P-MOS output.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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realtek,drive-strength-n:
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description: |
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Similar to the realtek,drive-strength-p, the realtek,drive-strength-n
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is used to control the driving strength of the N-MOS output.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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realtek,duty-cycle:
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description: |
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An integer describing the level to adjust output duty cycle, controlling
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the proportion of positive and negative waveforms in nanoseconds.
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Valid arguments are described as below:
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0: 0ns
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2: + 0.25ns
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3: + 0.5ns
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4: -0.25ns
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5: -0.5ns
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 2, 3, 4, 5 ]
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required:
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- pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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pinctrl@4e000 {
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compatible = "realtek,rtd1315e-pinctrl";
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reg = <0x4e000 0x130>;
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emmc-hs200-pins {
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pins = "emmc_clk",
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"emmc_cmd",
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"emmc_data_0",
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"emmc_data_1",
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"emmc_data_2",
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"emmc_data_3",
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"emmc_data_4",
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"emmc_data_5",
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"emmc_data_6",
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"emmc_data_7";
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function = "emmc";
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realtek,drive-strength-p = <0x2>;
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realtek,drive-strength-n = <0x2>;
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};
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i2c-0-pins {
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pins = "gpio_12",
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"gpio_13";
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function = "i2c0";
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drive-strength = <4>;
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};
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};
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