ath9k: Update BaseExtension_1 eeprom structure
* Add a new field "misc_enable" * Use int_8 for tempslopextension. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -139,7 +139,7 @@ static const struct ar9300_eeprom ar9300_default = {
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},
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.base_ext1 = {
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.ant_div_control = 0,
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.future = {0, 0, 0},
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.future = {0, 0},
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.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
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},
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.calFreqPier2G = {
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@ -717,7 +717,7 @@ static const struct ar9300_eeprom ar9300_x113 = {
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},
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.base_ext1 = {
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.ant_div_control = 0,
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.future = {0, 0, 0},
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.future = {0, 0},
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.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
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},
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.calFreqPier2G = {
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@ -1296,7 +1296,7 @@ static const struct ar9300_eeprom ar9300_h112 = {
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},
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.base_ext1 = {
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.ant_div_control = 0,
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.future = {0, 0, 0},
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.future = {0, 0},
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.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
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},
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.calFreqPier2G = {
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@ -1875,7 +1875,7 @@ static const struct ar9300_eeprom ar9300_x112 = {
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},
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.base_ext1 = {
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.ant_div_control = 0,
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.future = {0, 0, 0},
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.future = {0, 0},
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.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
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},
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.calFreqPier2G = {
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@ -2453,7 +2453,7 @@ static const struct ar9300_eeprom ar9300_h116 = {
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},
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.base_ext1 = {
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.ant_div_control = 0,
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.future = {0, 0, 0},
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.future = {0, 0},
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.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
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},
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.calFreqPier2G = {
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@ -270,10 +270,20 @@ struct cal_ctl_data_5g {
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u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
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} __packed;
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#define MAX_BASE_EXTENSION_FUTURE 2
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struct ar9300_BaseExtension_1 {
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u8 ant_div_control;
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u8 future[3];
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u8 tempslopextension[8];
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u8 future[MAX_BASE_EXTENSION_FUTURE];
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/*
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* misc_enable:
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*
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* BIT 0 - TX Gain Cap enable.
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* BIT 1 - Uncompressed Checksum enable.
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* BIT 2/3 - MinCCApwr enable 2g/5g.
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*/
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u8 misc_enable;
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int8_t tempslopextension[8];
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int8_t quick_drop_low;
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int8_t quick_drop_high;
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} __packed;
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