net: bcmgenet: add UMAC_IRQ_RXDMA_DONE and UMAC_IRQ_TXDMA_DONE
Add #define for UMAC_IRQ_RXDMA_DONE and UMAC_IRQ_TXDMA_DONE in order to simplify the code that handles Rx and Tx default queue interrupts. Signed-off-by: Petri Gynther <pgynther@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -966,15 +966,13 @@ static void bcmgenet_free_cb(struct enet_cb *cb)
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static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
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{
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bcmgenet_intrl2_0_writel(ring->priv,
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UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE,
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bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
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INTRL2_CPU_MASK_SET);
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}
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static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
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{
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bcmgenet_intrl2_0_writel(ring->priv,
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UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE,
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bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
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INTRL2_CPU_MASK_CLEAR);
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}
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@ -994,15 +992,13 @@ static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
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static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
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{
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bcmgenet_intrl2_0_writel(ring->priv,
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UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
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bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
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INTRL2_CPU_MASK_SET);
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}
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static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
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{
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bcmgenet_intrl2_0_writel(ring->priv,
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UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
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bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
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INTRL2_CPU_MASK_CLEAR);
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}
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@ -1727,10 +1723,10 @@ static int init_umac(struct bcmgenet_priv *priv)
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bcmgenet_intr_disable(priv);
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/* Enable Rx default queue 16 interrupts */
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int0_enable |= (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE);
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int0_enable |= UMAC_IRQ_RXDMA_DONE;
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/* Enable Tx default queue 16 interrupts */
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int0_enable |= (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE);
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int0_enable |= UMAC_IRQ_TXDMA_DONE;
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/* Monitor cable plug/unplugged event for internal PHY */
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if (phy_is_internal(priv->phydev)) {
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@ -2353,7 +2349,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
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netif_dbg(priv, intr, priv->dev,
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"IRQ=0x%x\n", priv->irq0_stat);
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if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
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if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
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rx_ring = &priv->rx_rings[DESC_INDEX];
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if (likely(napi_schedule_prep(&rx_ring->napi))) {
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@ -2362,7 +2358,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
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}
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}
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if (priv->irq0_stat & (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
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if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
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tx_ring = &priv->tx_rings[DESC_INDEX];
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if (likely(napi_schedule_prep(&tx_ring->napi))) {
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@ -303,9 +303,13 @@ struct bcmgenet_mib_counters {
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#define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
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#define UMAC_IRQ_RXDMA_PDONE (1 << 14)
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#define UMAC_IRQ_RXDMA_BDONE (1 << 15)
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#define UMAC_IRQ_RXDMA_DONE (UMAC_IRQ_RXDMA_PDONE | \
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UMAC_IRQ_RXDMA_BDONE)
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#define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
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#define UMAC_IRQ_TXDMA_PDONE (1 << 17)
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#define UMAC_IRQ_TXDMA_BDONE (1 << 18)
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#define UMAC_IRQ_TXDMA_DONE (UMAC_IRQ_TXDMA_PDONE | \
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UMAC_IRQ_TXDMA_BDONE)
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/* Only valid for GENETv3+ */
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#define UMAC_IRQ_MDIO_DONE (1 << 23)
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#define UMAC_IRQ_MDIO_ERROR (1 << 24)
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