MIPS: Save/restore MSA context around signals
This patch extends sigcontext in order to hold the most significant 64 bits of each vector register in addition to the MSA control & status register. The least significant 64 bits are already saved as the scalar FP context. This makes things a little awkward since the least & most significant 64 bits of each vector register are not contiguous in memory. Thus the copy_u & insert instructions are used to transfer the values of the most significant 64 bits via GP registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6533/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
a8ad136789
commit
eec43a224c
@ -32,6 +32,8 @@ struct sigcontext32 {
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__u32 sc_lo2;
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__u32 sc_hi3;
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__u32 sc_lo3;
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__u64 sc_msaregs[32]; /* Most significant 64 bits */
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__u32 sc_msa_csr;
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};
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
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#endif /* _ASM_SIGCONTEXT_H */
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@ -12,6 +12,10 @@
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#include <linux/types.h>
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#include <asm/sgidefs.h>
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/* Bits which may be set in sc_used_math */
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#define USEDMATH_FP (1 << 0)
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#define USEDMATH_MSA (1 << 1)
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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/*
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@ -37,6 +41,8 @@ struct sigcontext {
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unsigned long sc_lo2;
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unsigned long sc_hi3;
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unsigned long sc_lo3;
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unsigned long long sc_msaregs[32]; /* Most significant 64 bits */
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unsigned long sc_msa_csr;
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};
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
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@ -70,6 +76,8 @@ struct sigcontext {
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__u32 sc_used_math;
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__u32 sc_dsp;
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__u32 sc_reserved;
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__u64 sc_msaregs[32];
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__u32 sc_msa_csr;
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};
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@ -295,6 +295,7 @@ void output_sc_defines(void)
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OFFSET(SC_LO2, sigcontext, sc_lo2);
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OFFSET(SC_HI3, sigcontext, sc_hi3);
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OFFSET(SC_LO3, sigcontext, sc_lo3);
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OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
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BLANK();
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}
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#endif
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@ -309,6 +310,7 @@ void output_sc_defines(void)
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OFFSET(SC_MDLO, sigcontext, sc_mdlo);
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OFFSET(SC_PC, sigcontext, sc_pc);
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OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
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OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
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BLANK();
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}
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#endif
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@ -320,6 +322,7 @@ void output_sc32_defines(void)
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OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
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OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
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OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
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OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
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BLANK();
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}
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#endif
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@ -13,6 +13,7 @@
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* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/errno.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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@ -245,6 +246,218 @@ LEAF(_restore_fp_context32)
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END(_restore_fp_context32)
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#endif
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#ifdef CONFIG_CPU_HAS_MSA
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.macro save_sc_msareg wr, off, sc, tmp
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#ifdef CONFIG_64BIT
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copy_u_d \tmp, \wr, 1
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EX sd \tmp, (\off+(\wr*8))(\sc)
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#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
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copy_u_w \tmp, \wr, 2
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EX sw \tmp, (\off+(\wr*8)+0)(\sc)
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copy_u_w \tmp, \wr, 3
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EX sw \tmp, (\off+(\wr*8)+4)(\sc)
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#else /* CONFIG_CPU_BIG_ENDIAN */
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copy_u_w \tmp, \wr, 2
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EX sw \tmp, (\off+(\wr*8)+4)(\sc)
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copy_u_w \tmp, \wr, 3
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EX sw \tmp, (\off+(\wr*8)+0)(\sc)
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#endif
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.endm
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/*
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* int _save_msa_context(struct sigcontext *sc)
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*
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* Save the upper 64 bits of each vector register along with the MSA_CSR
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* register into sc. Returns zero on success, else non-zero.
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*/
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LEAF(_save_msa_context)
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save_sc_msareg 0, SC_MSAREGS, a0, t0
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save_sc_msareg 1, SC_MSAREGS, a0, t0
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save_sc_msareg 2, SC_MSAREGS, a0, t0
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save_sc_msareg 3, SC_MSAREGS, a0, t0
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save_sc_msareg 4, SC_MSAREGS, a0, t0
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save_sc_msareg 5, SC_MSAREGS, a0, t0
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save_sc_msareg 6, SC_MSAREGS, a0, t0
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save_sc_msareg 7, SC_MSAREGS, a0, t0
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save_sc_msareg 8, SC_MSAREGS, a0, t0
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save_sc_msareg 9, SC_MSAREGS, a0, t0
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save_sc_msareg 10, SC_MSAREGS, a0, t0
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save_sc_msareg 11, SC_MSAREGS, a0, t0
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save_sc_msareg 12, SC_MSAREGS, a0, t0
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save_sc_msareg 13, SC_MSAREGS, a0, t0
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save_sc_msareg 14, SC_MSAREGS, a0, t0
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save_sc_msareg 15, SC_MSAREGS, a0, t0
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save_sc_msareg 16, SC_MSAREGS, a0, t0
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save_sc_msareg 17, SC_MSAREGS, a0, t0
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save_sc_msareg 18, SC_MSAREGS, a0, t0
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save_sc_msareg 19, SC_MSAREGS, a0, t0
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save_sc_msareg 20, SC_MSAREGS, a0, t0
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save_sc_msareg 21, SC_MSAREGS, a0, t0
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save_sc_msareg 22, SC_MSAREGS, a0, t0
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save_sc_msareg 23, SC_MSAREGS, a0, t0
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save_sc_msareg 24, SC_MSAREGS, a0, t0
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save_sc_msareg 25, SC_MSAREGS, a0, t0
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save_sc_msareg 26, SC_MSAREGS, a0, t0
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save_sc_msareg 27, SC_MSAREGS, a0, t0
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save_sc_msareg 28, SC_MSAREGS, a0, t0
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save_sc_msareg 29, SC_MSAREGS, a0, t0
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save_sc_msareg 30, SC_MSAREGS, a0, t0
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save_sc_msareg 31, SC_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_save_msa_context)
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#ifdef CONFIG_MIPS32_COMPAT
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/*
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* int _save_msa_context32(struct sigcontext32 *sc)
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*
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* Save the upper 64 bits of each vector register along with the MSA_CSR
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* register into sc. Returns zero on success, else non-zero.
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*/
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LEAF(_save_msa_context32)
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save_sc_msareg 0, SC32_MSAREGS, a0, t0
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save_sc_msareg 1, SC32_MSAREGS, a0, t0
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save_sc_msareg 2, SC32_MSAREGS, a0, t0
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save_sc_msareg 3, SC32_MSAREGS, a0, t0
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save_sc_msareg 4, SC32_MSAREGS, a0, t0
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save_sc_msareg 5, SC32_MSAREGS, a0, t0
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save_sc_msareg 6, SC32_MSAREGS, a0, t0
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save_sc_msareg 7, SC32_MSAREGS, a0, t0
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save_sc_msareg 8, SC32_MSAREGS, a0, t0
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save_sc_msareg 9, SC32_MSAREGS, a0, t0
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save_sc_msareg 10, SC32_MSAREGS, a0, t0
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save_sc_msareg 11, SC32_MSAREGS, a0, t0
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save_sc_msareg 12, SC32_MSAREGS, a0, t0
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save_sc_msareg 13, SC32_MSAREGS, a0, t0
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save_sc_msareg 14, SC32_MSAREGS, a0, t0
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save_sc_msareg 15, SC32_MSAREGS, a0, t0
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save_sc_msareg 16, SC32_MSAREGS, a0, t0
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save_sc_msareg 17, SC32_MSAREGS, a0, t0
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save_sc_msareg 18, SC32_MSAREGS, a0, t0
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save_sc_msareg 19, SC32_MSAREGS, a0, t0
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save_sc_msareg 20, SC32_MSAREGS, a0, t0
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save_sc_msareg 21, SC32_MSAREGS, a0, t0
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save_sc_msareg 22, SC32_MSAREGS, a0, t0
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save_sc_msareg 23, SC32_MSAREGS, a0, t0
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save_sc_msareg 24, SC32_MSAREGS, a0, t0
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save_sc_msareg 25, SC32_MSAREGS, a0, t0
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save_sc_msareg 26, SC32_MSAREGS, a0, t0
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save_sc_msareg 27, SC32_MSAREGS, a0, t0
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save_sc_msareg 28, SC32_MSAREGS, a0, t0
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save_sc_msareg 29, SC32_MSAREGS, a0, t0
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save_sc_msareg 30, SC32_MSAREGS, a0, t0
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save_sc_msareg 31, SC32_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_save_msa_context32)
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#endif /* CONFIG_MIPS32_COMPAT */
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.macro restore_sc_msareg wr, off, sc, tmp
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#ifdef CONFIG_64BIT
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EX ld \tmp, (\off+(\wr*8))(\sc)
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insert_d \wr, 1, \tmp
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#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
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EX lw \tmp, (\off+(\wr*8)+0)(\sc)
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insert_w \wr, 2, \tmp
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EX lw \tmp, (\off+(\wr*8)+4)(\sc)
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insert_w \wr, 3, \tmp
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#else /* CONFIG_CPU_BIG_ENDIAN */
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EX lw \tmp, (\off+(\wr*8)+4)(\sc)
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insert_w \wr, 2, \tmp
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EX lw \tmp, (\off+(\wr*8)+0)(\sc)
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insert_w \wr, 3, \tmp
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#endif
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.endm
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/*
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* int _restore_msa_context(struct sigcontext *sc)
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*/
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LEAF(_restore_msa_context)
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restore_sc_msareg 0, SC_MSAREGS, a0, t0
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restore_sc_msareg 1, SC_MSAREGS, a0, t0
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restore_sc_msareg 2, SC_MSAREGS, a0, t0
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restore_sc_msareg 3, SC_MSAREGS, a0, t0
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restore_sc_msareg 4, SC_MSAREGS, a0, t0
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restore_sc_msareg 5, SC_MSAREGS, a0, t0
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restore_sc_msareg 6, SC_MSAREGS, a0, t0
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restore_sc_msareg 7, SC_MSAREGS, a0, t0
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restore_sc_msareg 8, SC_MSAREGS, a0, t0
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restore_sc_msareg 9, SC_MSAREGS, a0, t0
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restore_sc_msareg 10, SC_MSAREGS, a0, t0
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restore_sc_msareg 11, SC_MSAREGS, a0, t0
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restore_sc_msareg 12, SC_MSAREGS, a0, t0
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restore_sc_msareg 13, SC_MSAREGS, a0, t0
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restore_sc_msareg 14, SC_MSAREGS, a0, t0
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restore_sc_msareg 15, SC_MSAREGS, a0, t0
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restore_sc_msareg 16, SC_MSAREGS, a0, t0
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restore_sc_msareg 17, SC_MSAREGS, a0, t0
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restore_sc_msareg 18, SC_MSAREGS, a0, t0
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restore_sc_msareg 19, SC_MSAREGS, a0, t0
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restore_sc_msareg 20, SC_MSAREGS, a0, t0
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restore_sc_msareg 21, SC_MSAREGS, a0, t0
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restore_sc_msareg 22, SC_MSAREGS, a0, t0
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restore_sc_msareg 23, SC_MSAREGS, a0, t0
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restore_sc_msareg 24, SC_MSAREGS, a0, t0
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restore_sc_msareg 25, SC_MSAREGS, a0, t0
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restore_sc_msareg 26, SC_MSAREGS, a0, t0
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restore_sc_msareg 27, SC_MSAREGS, a0, t0
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restore_sc_msareg 28, SC_MSAREGS, a0, t0
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restore_sc_msareg 29, SC_MSAREGS, a0, t0
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restore_sc_msareg 30, SC_MSAREGS, a0, t0
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restore_sc_msareg 31, SC_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_restore_msa_context)
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#ifdef CONFIG_MIPS32_COMPAT
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/*
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* int _restore_msa_context32(struct sigcontext32 *sc)
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*/
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LEAF(_restore_msa_context32)
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restore_sc_msareg 0, SC32_MSAREGS, a0, t0
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restore_sc_msareg 1, SC32_MSAREGS, a0, t0
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restore_sc_msareg 2, SC32_MSAREGS, a0, t0
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restore_sc_msareg 3, SC32_MSAREGS, a0, t0
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restore_sc_msareg 4, SC32_MSAREGS, a0, t0
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restore_sc_msareg 5, SC32_MSAREGS, a0, t0
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restore_sc_msareg 6, SC32_MSAREGS, a0, t0
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restore_sc_msareg 7, SC32_MSAREGS, a0, t0
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restore_sc_msareg 8, SC32_MSAREGS, a0, t0
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restore_sc_msareg 9, SC32_MSAREGS, a0, t0
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restore_sc_msareg 10, SC32_MSAREGS, a0, t0
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restore_sc_msareg 11, SC32_MSAREGS, a0, t0
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restore_sc_msareg 12, SC32_MSAREGS, a0, t0
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restore_sc_msareg 13, SC32_MSAREGS, a0, t0
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restore_sc_msareg 14, SC32_MSAREGS, a0, t0
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restore_sc_msareg 15, SC32_MSAREGS, a0, t0
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restore_sc_msareg 16, SC32_MSAREGS, a0, t0
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restore_sc_msareg 17, SC32_MSAREGS, a0, t0
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restore_sc_msareg 18, SC32_MSAREGS, a0, t0
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restore_sc_msareg 19, SC32_MSAREGS, a0, t0
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restore_sc_msareg 20, SC32_MSAREGS, a0, t0
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restore_sc_msareg 21, SC32_MSAREGS, a0, t0
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restore_sc_msareg 22, SC32_MSAREGS, a0, t0
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restore_sc_msareg 23, SC32_MSAREGS, a0, t0
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restore_sc_msareg 24, SC32_MSAREGS, a0, t0
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restore_sc_msareg 25, SC32_MSAREGS, a0, t0
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restore_sc_msareg 26, SC32_MSAREGS, a0, t0
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restore_sc_msareg 27, SC32_MSAREGS, a0, t0
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restore_sc_msareg 28, SC32_MSAREGS, a0, t0
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restore_sc_msareg 29, SC32_MSAREGS, a0, t0
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restore_sc_msareg 30, SC32_MSAREGS, a0, t0
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restore_sc_msareg 31, SC32_MSAREGS, a0, t0
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jr ra
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li v0, 0
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END(_restore_msa_context32)
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#endif /* CONFIG_MIPS32_COMPAT */
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#endif /* CONFIG_CPU_HAS_MSA */
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.set reorder
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.type fault@function
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@ -30,6 +30,7 @@
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#include <linux/bitops.h>
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#include <asm/cacheflush.h>
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#include <asm/fpu.h>
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#include <asm/msa.h>
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#include <asm/sim.h>
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#include <asm/ucontext.h>
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#include <asm/cpu-features.h>
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@ -46,6 +47,9 @@ static int (*restore_fp_context)(struct sigcontext __user *sc);
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extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
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extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
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extern asmlinkage int _save_msa_context(struct sigcontext __user *sc);
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extern asmlinkage int _restore_msa_context(struct sigcontext __user *sc);
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struct sigframe {
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u32 sf_ass[4]; /* argument save space for o32 */
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u32 sf_pad[2]; /* Was: signal trampoline */
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@ -94,20 +98,60 @@ static int copy_fp_from_sigcontext(struct sigcontext __user *sc)
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return err;
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}
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/*
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* These functions will save only the upper 64 bits of the vector registers,
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* since the lower 64 bits have already been saved as the scalar FP context.
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*/
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static int copy_msa_to_sigcontext(struct sigcontext __user *sc)
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{
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int i;
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int err = 0;
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for (i = 0; i < NUM_FPU_REGS; i++) {
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err |=
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__put_user(get_fpr64(¤t->thread.fpu.fpr[i], 1),
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&sc->sc_msaregs[i]);
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}
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err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
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return err;
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}
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static int copy_msa_from_sigcontext(struct sigcontext __user *sc)
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{
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int i;
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int err = 0;
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u64 val;
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for (i = 0; i < NUM_FPU_REGS; i++) {
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err |= __get_user(val, &sc->sc_msaregs[i]);
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set_fpr64(¤t->thread.fpu.fpr[i], 1, val);
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}
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err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
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return err;
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}
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/*
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* Helper routines
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*/
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static int protected_save_fp_context(struct sigcontext __user *sc)
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static int protected_save_fp_context(struct sigcontext __user *sc,
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unsigned used_math)
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{
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int err;
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bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
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while (1) {
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lock_fpu_owner();
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if (is_fpu_owner()) {
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err = save_fp_context(sc);
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if (save_msa && !err)
|
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err = _save_msa_context(sc);
|
||||
unlock_fpu_owner();
|
||||
} else {
|
||||
unlock_fpu_owner();
|
||||
err = copy_fp_to_sigcontext(sc);
|
||||
if (save_msa && !err)
|
||||
err = copy_msa_to_sigcontext(sc);
|
||||
}
|
||||
if (likely(!err))
|
||||
break;
|
||||
@ -121,17 +165,28 @@ static int protected_save_fp_context(struct sigcontext __user *sc)
|
||||
return err;
|
||||
}
|
||||
|
||||
static int protected_restore_fp_context(struct sigcontext __user *sc)
|
||||
static int protected_restore_fp_context(struct sigcontext __user *sc,
|
||||
unsigned used_math)
|
||||
{
|
||||
int err, tmp __maybe_unused;
|
||||
bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
|
||||
while (1) {
|
||||
lock_fpu_owner();
|
||||
if (is_fpu_owner()) {
|
||||
err = restore_fp_context(sc);
|
||||
if (restore_msa && !err) {
|
||||
enable_msa();
|
||||
err = _restore_msa_context(sc);
|
||||
} else {
|
||||
/* signal handler may have used MSA */
|
||||
disable_msa();
|
||||
}
|
||||
unlock_fpu_owner();
|
||||
} else {
|
||||
unlock_fpu_owner();
|
||||
err = copy_fp_from_sigcontext(sc);
|
||||
if (!err && (used_math & USEDMATH_MSA))
|
||||
err = copy_msa_from_sigcontext(sc);
|
||||
}
|
||||
if (likely(!err))
|
||||
break;
|
||||
@ -172,7 +227,8 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
|
||||
err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
|
||||
}
|
||||
|
||||
used_math = !!used_math();
|
||||
used_math = used_math() ? USEDMATH_FP : 0;
|
||||
used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
|
||||
err |= __put_user(used_math, &sc->sc_used_math);
|
||||
|
||||
if (used_math) {
|
||||
@ -180,7 +236,7 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
|
||||
* Save FPU state to signal context. Signal handler
|
||||
* will "inherit" current FPU state.
|
||||
*/
|
||||
err |= protected_save_fp_context(sc);
|
||||
err |= protected_save_fp_context(sc, used_math);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
@ -205,14 +261,14 @@ int fpcsr_pending(unsigned int __user *fpcsr)
|
||||
}
|
||||
|
||||
static int
|
||||
check_and_restore_fp_context(struct sigcontext __user *sc)
|
||||
check_and_restore_fp_context(struct sigcontext __user *sc, unsigned used_math)
|
||||
{
|
||||
int err, sig;
|
||||
|
||||
err = sig = fpcsr_pending(&sc->sc_fpc_csr);
|
||||
if (err > 0)
|
||||
err = 0;
|
||||
err |= protected_restore_fp_context(sc);
|
||||
err |= protected_restore_fp_context(sc, used_math);
|
||||
return err ?: sig;
|
||||
}
|
||||
|
||||
@ -252,9 +308,10 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
|
||||
if (used_math) {
|
||||
/* restore fpu context if we have used it before */
|
||||
if (!err)
|
||||
err = check_and_restore_fp_context(sc);
|
||||
err = check_and_restore_fp_context(sc, used_math);
|
||||
} else {
|
||||
/* signal handler may have used FPU. Give it up. */
|
||||
/* signal handler may have used FPU or MSA. Disable them. */
|
||||
disable_msa();
|
||||
lose_fpu(0);
|
||||
}
|
||||
|
||||
|
||||
@ -30,6 +30,7 @@
|
||||
#include <asm/sim.h>
|
||||
#include <asm/ucontext.h>
|
||||
#include <asm/fpu.h>
|
||||
#include <asm/msa.h>
|
||||
#include <asm/war.h>
|
||||
#include <asm/vdso.h>
|
||||
#include <asm/dsp.h>
|
||||
@ -42,6 +43,9 @@ static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
|
||||
extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
|
||||
extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
|
||||
|
||||
extern asmlinkage int _save_msa_context32(struct sigcontext32 __user *sc);
|
||||
extern asmlinkage int _restore_msa_context32(struct sigcontext32 __user *sc);
|
||||
|
||||
/*
|
||||
* Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
|
||||
*/
|
||||
@ -110,20 +114,60 @@ static int copy_fp_from_sigcontext32(struct sigcontext32 __user *sc)
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* These functions will save only the upper 64 bits of the vector registers,
|
||||
* since the lower 64 bits have already been saved as the scalar FP context.
|
||||
*/
|
||||
static int copy_msa_to_sigcontext32(struct sigcontext32 __user *sc)
|
||||
{
|
||||
int i;
|
||||
int err = 0;
|
||||
|
||||
for (i = 0; i < NUM_FPU_REGS; i++) {
|
||||
err |=
|
||||
__put_user(get_fpr64(¤t->thread.fpu.fpr[i], 1),
|
||||
&sc->sc_msaregs[i]);
|
||||
}
|
||||
err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int copy_msa_from_sigcontext32(struct sigcontext32 __user *sc)
|
||||
{
|
||||
int i;
|
||||
int err = 0;
|
||||
u64 val;
|
||||
|
||||
for (i = 0; i < NUM_FPU_REGS; i++) {
|
||||
err |= __get_user(val, &sc->sc_msaregs[i]);
|
||||
set_fpr64(¤t->thread.fpu.fpr[i], 1, val);
|
||||
}
|
||||
err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* sigcontext handlers
|
||||
*/
|
||||
static int protected_save_fp_context32(struct sigcontext32 __user *sc)
|
||||
static int protected_save_fp_context32(struct sigcontext32 __user *sc,
|
||||
unsigned used_math)
|
||||
{
|
||||
int err;
|
||||
bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
|
||||
while (1) {
|
||||
lock_fpu_owner();
|
||||
if (is_fpu_owner()) {
|
||||
err = save_fp_context32(sc);
|
||||
if (save_msa && !err)
|
||||
err = _save_msa_context32(sc);
|
||||
unlock_fpu_owner();
|
||||
} else {
|
||||
unlock_fpu_owner();
|
||||
err = copy_fp_to_sigcontext32(sc);
|
||||
if (save_msa && !err)
|
||||
err = copy_msa_to_sigcontext32(sc);
|
||||
}
|
||||
if (likely(!err))
|
||||
break;
|
||||
@ -137,17 +181,28 @@ static int protected_save_fp_context32(struct sigcontext32 __user *sc)
|
||||
return err;
|
||||
}
|
||||
|
||||
static int protected_restore_fp_context32(struct sigcontext32 __user *sc)
|
||||
static int protected_restore_fp_context32(struct sigcontext32 __user *sc,
|
||||
unsigned used_math)
|
||||
{
|
||||
int err, tmp __maybe_unused;
|
||||
bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
|
||||
while (1) {
|
||||
lock_fpu_owner();
|
||||
if (is_fpu_owner()) {
|
||||
err = restore_fp_context32(sc);
|
||||
if (restore_msa && !err) {
|
||||
enable_msa();
|
||||
err = _restore_msa_context32(sc);
|
||||
} else {
|
||||
/* signal handler may have used MSA */
|
||||
disable_msa();
|
||||
}
|
||||
unlock_fpu_owner();
|
||||
} else {
|
||||
unlock_fpu_owner();
|
||||
err = copy_fp_from_sigcontext32(sc);
|
||||
if (restore_msa && !err)
|
||||
err = copy_msa_from_sigcontext32(sc);
|
||||
}
|
||||
if (likely(!err))
|
||||
break;
|
||||
@ -186,7 +241,8 @@ static int setup_sigcontext32(struct pt_regs *regs,
|
||||
err |= __put_user(mflo3(), &sc->sc_lo3);
|
||||
}
|
||||
|
||||
used_math = !!used_math();
|
||||
used_math = used_math() ? USEDMATH_FP : 0;
|
||||
used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
|
||||
err |= __put_user(used_math, &sc->sc_used_math);
|
||||
|
||||
if (used_math) {
|
||||
@ -194,20 +250,21 @@ static int setup_sigcontext32(struct pt_regs *regs,
|
||||
* Save FPU state to signal context. Signal handler
|
||||
* will "inherit" current FPU state.
|
||||
*/
|
||||
err |= protected_save_fp_context32(sc);
|
||||
err |= protected_save_fp_context32(sc, used_math);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
check_and_restore_fp_context32(struct sigcontext32 __user *sc)
|
||||
check_and_restore_fp_context32(struct sigcontext32 __user *sc,
|
||||
unsigned used_math)
|
||||
{
|
||||
int err, sig;
|
||||
|
||||
err = sig = fpcsr_pending(&sc->sc_fpc_csr);
|
||||
if (err > 0)
|
||||
err = 0;
|
||||
err |= protected_restore_fp_context32(sc);
|
||||
err |= protected_restore_fp_context32(sc, used_math);
|
||||
return err ?: sig;
|
||||
}
|
||||
|
||||
@ -244,9 +301,10 @@ static int restore_sigcontext32(struct pt_regs *regs,
|
||||
if (used_math) {
|
||||
/* restore fpu context if we have used it before */
|
||||
if (!err)
|
||||
err = check_and_restore_fp_context32(sc);
|
||||
err = check_and_restore_fp_context32(sc, used_math);
|
||||
} else {
|
||||
/* signal handler may have used FPU. Give it up. */
|
||||
/* signal handler may have used FPU or MSA. Disable them. */
|
||||
disable_msa();
|
||||
lose_fpu(0);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user