arm64: dts: qcom: msm8996: Add device tree entries to support crypto engine
The change adds description of Qualcomm crypto engine controller and BAM associated with it. The change is inspired by commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine.") While performance of cryptographic algorithms executed on QCE is lower than e.g. ones tinkered for ARM NEON, the offloaded execution would make sense: # cryptsetup benchmark | grep aes aes-cbc 128b 71.0 MiB/s 71.9 MiB/s aes-cbc 256b 62.4 MiB/s 62.4 MiB/s aes-xts 256b 70.7 MiB/s 70.8 MiB/s aes-xts 512b 62.0 MiB/s 63.3 MiB/s Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Thara Gopinath <thara.gopinath@linaro.org> Acked-by: Thara Gopinath <thara.gopinath@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211011094822.1580122-1-vladimir.zapolskiy@linaro.org
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@ -705,6 +705,28 @@
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#thermal-sensor-cells = <1>;
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};
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cryptobam: dma@644000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00644000 0x24000>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CE1_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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qcom,controlled-remotely = <1>;
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};
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crypto: crypto@67a000 {
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compatible = "qcom,crypto-v5.4";
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reg = <0x0067a000 0x6000>;
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clocks = <&gcc GCC_CE1_AHB_CLK>,
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<&gcc GCC_CE1_AXI_CLK>,
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<&gcc GCC_CE1_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 6>, <&cryptobam 7>;
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dma-names = "rx", "tx";
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};
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tcsr_mutex_regs: syscon@740000 {
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compatible = "syscon";
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reg = <0x00740000 0x40000>;
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