drm/radeon: add set_uvd_clocks callback for r7xx v3
v2: avoid 64bit divide v3: rv740 uses the evegreen upll configuration Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Christian König
Alex Deucher
parent
2539eb02de
commit
ef0e6e657c
@ -1183,6 +1183,7 @@ static struct radeon_asic rv770_asic = {
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.get_pcie_lanes = &r600_get_pcie_lanes,
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.set_pcie_lanes = &r600_set_pcie_lanes,
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.set_clock_gating = &radeon_atom_set_clock_gating,
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.set_uvd_clocks = &rv770_set_uvd_clocks,
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},
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.pflip = {
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.pre_page_flip = &rs600_pre_page_flip,
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@ -424,6 +424,7 @@ int rv770_copy_dma(struct radeon_device *rdev,
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struct radeon_fence **fence);
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u32 rv770_get_xclk(struct radeon_device *rdev);
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int rv770_uvd_resume(struct radeon_device *rdev);
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int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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/*
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* evergreen
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@ -42,6 +42,162 @@
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static void rv770_gpu_init(struct radeon_device *rdev);
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void rv770_fini(struct radeon_device *rdev);
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static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
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int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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static int rv770_uvd_calc_post_div(unsigned target_freq,
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unsigned vco_freq,
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unsigned *div)
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{
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/* Fclk = Fvco / PDIV */
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*div = vco_freq / target_freq;
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/* we alway need a frequency less than or equal the target */
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if ((vco_freq / *div) > target_freq)
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*div += 1;
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/* out of range ? */
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if (*div > 30)
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return -1; /* forget it */
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*div -= 1;
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return vco_freq / (*div + 1);
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}
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static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev)
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{
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unsigned i;
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/* assert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
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/* wait for CTLACK and CTLACK2 to get asserted */
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for (i = 0; i < 100; ++i) {
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uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
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if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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/* deassert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
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return 0;
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}
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int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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{
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/* start off with something large */
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int optimal_diff_score = 0x7FFFFFF;
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unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
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unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
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unsigned vco_freq, vco_min = 50000, vco_max = 160000;
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unsigned ref_freq = rdev->clock.spll.reference_freq;
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int r;
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/* RV740 uses evergreen uvd clk programming */
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if (rdev->family == CHIP_RV740)
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return evergreen_set_uvd_clocks(rdev, vclk, dclk);
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/* loop through vco from low to high */
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vco_min = max(max(vco_min, vclk), dclk);
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for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) {
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uint64_t fb_div = (uint64_t)vco_freq * 43663;
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int calc_clk, diff_score, diff_vclk, diff_dclk;
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unsigned vclk_div, dclk_div;
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do_div(fb_div, ref_freq);
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fb_div |= 1;
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/* fb div out of range ? */
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if (fb_div > 0x03FFFFFF)
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break; /* it can oly get worse */
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/* calc vclk with current vco freq. */
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calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_vclk = vclk - calc_clk;
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/* calc dclk with current vco freq. */
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calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_dclk = dclk - calc_clk;
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/* determine if this vco setting is better than current optimal settings */
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diff_score = abs(diff_vclk) + abs(diff_dclk);
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if (diff_score < optimal_diff_score) {
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optimal_fb_div = fb_div;
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optimal_vclk_div = vclk_div;
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optimal_dclk_div = dclk_div;
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optimal_vco_freq = vco_freq;
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optimal_diff_score = diff_score;
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if (optimal_diff_score == 0)
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break; /* it can't get better than this */
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}
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}
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* set UPLL_FB_DIV to 0x50000 */
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
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/* deassert UPLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
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/* assert BYPASS EN and FB_DIV[0] <- ??? why? */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
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r = rv770_uvd_send_upll_ctlreq(rdev);
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if (r)
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return r;
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/* assert PLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
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/* set the required FB_DIV, REF_DIV, Post divder values */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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UPLL_SW_HILEN(optimal_vclk_div >> 1) |
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UPLL_SW_LOLEN((optimal_vclk_div >> 1) + (optimal_vclk_div & 1)) |
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UPLL_SW_HILEN2(optimal_dclk_div >> 1) |
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UPLL_SW_LOLEN2((optimal_dclk_div >> 1) + (optimal_dclk_div & 1)),
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~UPLL_SW_MASK);
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div),
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~UPLL_FB_DIV_MASK);
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/* give the PLL some time to settle */
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mdelay(15);
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/* deassert PLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
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mdelay(15);
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/* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
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WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
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r = rv770_uvd_send_upll_ctlreq(rdev);
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if (r)
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return r;
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/* switch VCLK and DCLK selection */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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mdelay(100);
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return 0;
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}
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#define PCIE_BUS_CLK 10000
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#define TCLK (PCIE_BUS_CLK / 10)
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@ -38,6 +38,30 @@
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#define R7XX_MAX_PIPES 8
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#define R7XX_MAX_PIPES_MASK 0xff
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/* discrete uvd clocks */
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#define CG_UPLL_FUNC_CNTL 0x718
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# define UPLL_RESET_MASK 0x00000001
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# define UPLL_SLEEP_MASK 0x00000002
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# define UPLL_BYPASS_EN_MASK 0x00000004
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# define UPLL_CTLREQ_MASK 0x00000008
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# define UPLL_REF_DIV(x) ((x) << 16)
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# define UPLL_REF_DIV_MASK 0x001F0000
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# define UPLL_CTLACK_MASK 0x40000000
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# define UPLL_CTLACK2_MASK 0x80000000
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#define CG_UPLL_FUNC_CNTL_2 0x71c
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# define UPLL_SW_HILEN(x) ((x) << 0)
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# define UPLL_SW_LOLEN(x) ((x) << 4)
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# define UPLL_SW_HILEN2(x) ((x) << 8)
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# define UPLL_SW_LOLEN2(x) ((x) << 12)
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# define UPLL_SW_MASK 0x0000FFFF
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# define VCLK_SRC_SEL(x) ((x) << 20)
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# define VCLK_SRC_SEL_MASK 0x01F00000
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# define DCLK_SRC_SEL(x) ((x) << 25)
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# define DCLK_SRC_SEL_MASK 0x3E000000
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#define CG_UPLL_FUNC_CNTL_3 0x720
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# define UPLL_FB_DIV(x) ((x) << 0)
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# define UPLL_FB_DIV_MASK 0x01FFFFFF
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/* Registers */
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#define CB_COLOR0_BASE 0x28040
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#define CB_COLOR1_BASE 0x28044
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