clk: rockchip: Add support for multiple clock providers
There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Xing Zheng
Heiko Stuebner
parent
268aebaa24
commit
ef1d9feecc
@ -46,6 +46,8 @@ struct rockchip_clk_pll {
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const struct rockchip_pll_rate_table *rate_table;
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unsigned int rate_count;
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spinlock_t *lock;
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struct rockchip_clk_provider *ctx;
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};
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#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
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@ -90,7 +92,7 @@ static long rockchip_pll_round_rate(struct clk_hw *hw,
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*/
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static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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struct regmap *grf = rockchip_clk_get_grf();
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struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
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unsigned int val;
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int delay = 24000000, ret;
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@ -251,7 +253,7 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate;
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unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
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struct regmap *grf = rockchip_clk_get_grf();
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struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
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if (IS_ERR(grf)) {
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pr_debug("%s: grf regmap not available, aborting rate change\n",
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@ -490,7 +492,7 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate;
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unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
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struct regmap *grf = rockchip_clk_get_grf();
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struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
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if (IS_ERR(grf)) {
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pr_debug("%s: grf regmap not available, aborting rate change\n",
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@ -563,7 +565,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)
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rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
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if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
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|| rate->nb != cur.nb) {
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struct regmap *grf = rockchip_clk_get_grf();
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struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
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if (IS_ERR(grf))
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return;
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@ -595,12 +597,13 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
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* Common registering of pll clocks
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*/
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struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
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struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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enum rockchip_pll_type pll_type,
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const char *name, const char *const *parent_names,
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u8 num_parents, void __iomem *base, int con_offset,
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int grf_lock_offset, int lock_shift, int mode_offset,
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int mode_shift, struct rockchip_pll_rate_table *rate_table,
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u8 clk_pll_flags, spinlock_t *lock)
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u8 num_parents, int con_offset, int grf_lock_offset,
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int lock_shift, int mode_offset, int mode_shift,
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struct rockchip_pll_rate_table *rate_table,
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u8 clk_pll_flags)
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{
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const char *pll_parents[3];
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struct clk_init_data init;
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@ -624,11 +627,11 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
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/* create the mux on top of the real pll */
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pll->pll_mux_ops = &clk_mux_ops;
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pll_mux = &pll->pll_mux;
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pll_mux->reg = base + mode_offset;
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pll_mux->reg = ctx->reg_base + mode_offset;
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pll_mux->shift = mode_shift;
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pll_mux->mask = PLL_MODE_MASK;
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pll_mux->flags = 0;
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pll_mux->lock = lock;
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pll_mux->lock = &ctx->lock;
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pll_mux->hw.init = &init;
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if (pll_type == pll_rk3036 || pll_type == pll_rk3066)
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@ -695,11 +698,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
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pll->hw.init = &init;
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pll->type = pll_type;
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pll->reg_base = base + con_offset;
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pll->reg_base = ctx->reg_base + con_offset;
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pll->lock_offset = grf_lock_offset;
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pll->lock_shift = lock_shift;
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pll->flags = clk_pll_flags;
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pll->lock = lock;
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pll->lock = &ctx->lock;
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pll->ctx = ctx;
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pll_clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(pll_clk)) {
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@ -440,6 +440,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {
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static void __init rk3036_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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@ -449,22 +450,26 @@ static void __init rk3036_clk_init(struct device_node *np)
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return;
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}
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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return;
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}
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clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock usb480m: %ld\n",
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__func__, PTR_ERR(clk));
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rockchip_clk_register_plls(rk3036_pll_clks,
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rockchip_clk_register_plls(ctx, rk3036_pll_clks,
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ARRAY_SIZE(rk3036_pll_clks),
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RK3036_GRF_SOC_STATUS0);
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rockchip_clk_register_branches(rk3036_clk_branches,
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rockchip_clk_register_branches(ctx, rk3036_clk_branches,
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ARRAY_SIZE(rk3036_clk_branches));
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rockchip_clk_protect_critical(rk3036_critical_clocks,
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ARRAY_SIZE(rk3036_critical_clocks));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3036_cpuclk_data, rk3036_cpuclk_rates,
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ARRAY_SIZE(rk3036_cpuclk_rates));
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@ -472,6 +477,8 @@ static void __init rk3036_clk_init(struct device_node *np)
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rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
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rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
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@ -759,57 +759,74 @@ static const char *const rk3188_critical_clocks[] __initconst = {
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"hclk_cpubus"
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};
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static void __init rk3188_common_clk_init(struct device_node *np)
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static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: could not map cru region\n", __func__);
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return;
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return ERR_PTR(-ENOMEM);
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}
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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rockchip_clk_register_branches(common_clk_branches,
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rockchip_clk_register_branches(ctx, common_clk_branches,
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ARRAY_SIZE(common_clk_branches));
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rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
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rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
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return ctx;
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}
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static void __init rk3066a_clk_init(struct device_node *np)
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{
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rk3188_common_clk_init(np);
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rockchip_clk_register_plls(rk3066_pll_clks,
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struct rockchip_clk_provider *ctx;
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ctx = rk3188_common_clk_init(np);
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if (IS_ERR(ctx))
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return;
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rockchip_clk_register_plls(ctx, rk3066_pll_clks,
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ARRAY_SIZE(rk3066_pll_clks),
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RK3066_GRF_SOC_STATUS);
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rockchip_clk_register_branches(rk3066a_clk_branches,
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rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
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ARRAY_SIZE(rk3066a_clk_branches));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3066_cpuclk_data, rk3066_cpuclk_rates,
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ARRAY_SIZE(rk3066_cpuclk_rates));
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rockchip_clk_protect_critical(rk3188_critical_clocks,
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ARRAY_SIZE(rk3188_critical_clocks));
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
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static void __init rk3188a_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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struct clk *clk1, *clk2;
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unsigned long rate;
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int ret;
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rk3188_common_clk_init(np);
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rockchip_clk_register_plls(rk3188_pll_clks,
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ctx = rk3188_common_clk_init(np);
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if (IS_ERR(ctx))
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return;
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rockchip_clk_register_plls(ctx, rk3188_pll_clks,
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ARRAY_SIZE(rk3188_pll_clks),
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RK3188_GRF_SOC_STATUS);
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rockchip_clk_register_branches(rk3188_clk_branches,
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rockchip_clk_register_branches(ctx, rk3188_clk_branches,
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ARRAY_SIZE(rk3188_clk_branches));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3188_cpuclk_data, rk3188_cpuclk_rates,
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ARRAY_SIZE(rk3188_cpuclk_rates));
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@ -833,6 +850,7 @@ static void __init rk3188a_clk_init(struct device_node *np)
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rockchip_clk_protect_critical(rk3188_critical_clocks,
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ARRAY_SIZE(rk3188_critical_clocks));
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
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@ -628,6 +628,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
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static void __init rk3228_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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@ -636,17 +637,21 @@ static void __init rk3228_clk_init(struct device_node *np)
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return;
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}
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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return;
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}
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rockchip_clk_register_plls(rk3228_pll_clks,
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rockchip_clk_register_plls(ctx, rk3228_pll_clks,
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ARRAY_SIZE(rk3228_pll_clks),
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RK3228_GRF_SOC_STATUS0);
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rockchip_clk_register_branches(rk3228_clk_branches,
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rockchip_clk_register_branches(ctx, rk3228_clk_branches,
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ARRAY_SIZE(rk3228_clk_branches));
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rockchip_clk_protect_critical(rk3228_critical_clocks,
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ARRAY_SIZE(rk3228_critical_clocks));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3228_cpuclk_data, rk3228_cpuclk_rates,
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ARRAY_SIZE(rk3228_cpuclk_rates));
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@ -654,6 +659,8 @@ static void __init rk3228_clk_init(struct device_node *np)
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rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);
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rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
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@ -881,6 +881,7 @@ static struct syscore_ops rk3288_clk_syscore_ops = {
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static void __init rk3288_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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struct clk *clk;
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rk3288_cru_base = of_iomap(np, 0);
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@ -889,7 +890,11 @@ static void __init rk3288_clk_init(struct device_node *np)
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return;
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}
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rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
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ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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return;
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}
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/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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@ -897,17 +902,17 @@ static void __init rk3288_clk_init(struct device_node *np)
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(clk, PCLK_WDT);
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(rk3288_pll_clks,
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rockchip_clk_register_plls(ctx, rk3288_pll_clks,
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ARRAY_SIZE(rk3288_pll_clks),
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RK3288_GRF_SOC_STATUS1);
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rockchip_clk_register_branches(rk3288_clk_branches,
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rockchip_clk_register_branches(ctx, rk3288_clk_branches,
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ARRAY_SIZE(rk3288_clk_branches));
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rockchip_clk_protect_critical(rk3288_critical_clocks,
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ARRAY_SIZE(rk3288_critical_clocks));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3288_cpuclk_data, rk3288_cpuclk_rates,
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ARRAY_SIZE(rk3288_cpuclk_rates));
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@ -916,8 +921,10 @@ static void __init rk3288_clk_init(struct device_node *np)
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rk3288_cru_base + RK3288_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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rockchip_register_restart_notifier(RK3288_GLB_SRST_FST,
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rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
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rk3288_clk_shutdown);
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register_syscore_ops(&rk3288_clk_syscore_ops);
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
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@ -862,6 +862,7 @@ static const char *const rk3368_critical_clocks[] __initconst = {
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static void __init rk3368_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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@ -871,7 +872,11 @@ static void __init rk3368_clk_init(struct device_node *np)
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return;
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}
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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return;
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}
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/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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@ -879,22 +884,22 @@ static void __init rk3368_clk_init(struct device_node *np)
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(clk, PCLK_WDT);
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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|
||||
rockchip_clk_register_plls(rk3368_pll_clks,
|
||||
rockchip_clk_register_plls(ctx, rk3368_pll_clks,
|
||||
ARRAY_SIZE(rk3368_pll_clks),
|
||||
RK3368_GRF_SOC_STATUS0);
|
||||
rockchip_clk_register_branches(rk3368_clk_branches,
|
||||
rockchip_clk_register_branches(ctx, rk3368_clk_branches,
|
||||
ARRAY_SIZE(rk3368_clk_branches));
|
||||
rockchip_clk_protect_critical(rk3368_critical_clocks,
|
||||
ARRAY_SIZE(rk3368_critical_clocks));
|
||||
|
||||
rockchip_clk_register_armclk(ARMCLKB, "armclkb",
|
||||
rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
|
||||
mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
|
||||
&rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
|
||||
ARRAY_SIZE(rk3368_cpuclkb_rates));
|
||||
|
||||
rockchip_clk_register_armclk(ARMCLKL, "armclkl",
|
||||
rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
|
||||
mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
|
||||
&rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
|
||||
ARRAY_SIZE(rk3368_cpuclkl_rates));
|
||||
@ -902,6 +907,8 @@ static void __init rk3368_clk_init(struct device_node *np)
|
||||
rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL);
|
||||
rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
|
||||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
|
||||
|
||||
@ -2,6 +2,9 @@
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
*
|
||||
* based on
|
||||
*
|
||||
* samsung/clk.c
|
||||
@ -157,7 +160,8 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
|
||||
return notifier_from_errno(ret);
|
||||
}
|
||||
|
||||
static struct clk *rockchip_clk_register_frac_branch(const char *name,
|
||||
static struct clk *rockchip_clk_register_frac_branch(
|
||||
struct rockchip_clk_provider *ctx, const char *name,
|
||||
const char *const *parent_names, u8 num_parents,
|
||||
void __iomem *base, int muxdiv_offset, u8 div_flags,
|
||||
int gate_offset, u8 gate_shift, u8 gate_flags,
|
||||
@ -250,7 +254,7 @@ static struct clk *rockchip_clk_register_frac_branch(const char *name,
|
||||
if (IS_ERR(mux_clk))
|
||||
return clk;
|
||||
|
||||
rockchip_clk_add_lookup(mux_clk, child->id);
|
||||
rockchip_clk_add_lookup(ctx, mux_clk, child->id);
|
||||
|
||||
/* notifier on the fraction divider to catch rate changes */
|
||||
if (frac->mux_frac_idx >= 0) {
|
||||
@ -314,66 +318,94 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
||||
return clk;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
static struct clk **clk_table;
|
||||
static void __iomem *reg_base;
|
||||
static struct clk_onecell_data clk_data;
|
||||
static struct device_node *cru_node;
|
||||
static struct regmap *grf;
|
||||
|
||||
void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks)
|
||||
struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
|
||||
void __iomem *base, unsigned long nr_clks)
|
||||
{
|
||||
reg_base = base;
|
||||
cru_node = np;
|
||||
grf = ERR_PTR(-EPROBE_DEFER);
|
||||
struct rockchip_clk_provider *ctx;
|
||||
struct clk **clk_table;
|
||||
int i;
|
||||
|
||||
ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
|
||||
if (!ctx) {
|
||||
pr_err("%s: Could not allocate clock provider context\n",
|
||||
__func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
pr_err("%s: could not allocate clock lookup table\n", __func__);
|
||||
if (!clk_table) {
|
||||
pr_err("%s: Could not allocate clock lookup table\n",
|
||||
__func__);
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
clk_data.clks = clk_table;
|
||||
clk_data.clk_num = nr_clks;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
for (i = 0; i < nr_clks; ++i)
|
||||
clk_table[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
ctx->reg_base = base;
|
||||
ctx->clk_data.clks = clk_table;
|
||||
ctx->clk_data.clk_num = nr_clks;
|
||||
ctx->cru_node = np;
|
||||
ctx->grf = ERR_PTR(-EPROBE_DEFER);
|
||||
spin_lock_init(&ctx->lock);
|
||||
|
||||
return ctx;
|
||||
|
||||
err_free:
|
||||
kfree(ctx);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
struct regmap *rockchip_clk_get_grf(void)
|
||||
void __init rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx)
|
||||
{
|
||||
if (IS_ERR(grf))
|
||||
grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
|
||||
return grf;
|
||||
if (np) {
|
||||
if (of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
&ctx->clk_data))
|
||||
pr_err("%s: could not register clk provider\n", __func__);
|
||||
}
|
||||
}
|
||||
|
||||
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
|
||||
struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx)
|
||||
{
|
||||
if (clk_table && id)
|
||||
clk_table[id] = clk;
|
||||
if (IS_ERR(ctx->grf))
|
||||
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf");
|
||||
return ctx->grf;
|
||||
}
|
||||
|
||||
void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
|
||||
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
struct clk *clk, unsigned int id)
|
||||
{
|
||||
if (ctx->clk_data.clks && id)
|
||||
ctx->clk_data.clks[id] = clk;
|
||||
}
|
||||
|
||||
void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_pll_clock *list,
|
||||
unsigned int nr_pll, int grf_lock_offset)
|
||||
{
|
||||
struct clk *clk;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < nr_pll; idx++, list++) {
|
||||
clk = rockchip_clk_register_pll(list->type, list->name,
|
||||
clk = rockchip_clk_register_pll(ctx, list->type, list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
reg_base, list->con_offset, grf_lock_offset,
|
||||
list->con_offset, grf_lock_offset,
|
||||
list->lock_shift, list->mode_offset,
|
||||
list->mode_shift, list->rate_table,
|
||||
list->pll_flags, &clk_lock);
|
||||
list->pll_flags);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
rockchip_clk_add_lookup(clk, list->id);
|
||||
rockchip_clk_add_lookup(ctx, clk, list->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init rockchip_clk_register_branches(
|
||||
struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
@ -389,56 +421,56 @@ void __init rockchip_clk_register_branches(
|
||||
case branch_mux:
|
||||
clk = clk_register_mux(NULL, list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
flags, reg_base + list->muxdiv_offset,
|
||||
flags, ctx->reg_base + list->muxdiv_offset,
|
||||
list->mux_shift, list->mux_width,
|
||||
list->mux_flags, &clk_lock);
|
||||
list->mux_flags, &ctx->lock);
|
||||
break;
|
||||
case branch_divider:
|
||||
if (list->div_table)
|
||||
clk = clk_register_divider_table(NULL,
|
||||
list->name, list->parent_names[0],
|
||||
flags, reg_base + list->muxdiv_offset,
|
||||
flags, ctx->reg_base + list->muxdiv_offset,
|
||||
list->div_shift, list->div_width,
|
||||
list->div_flags, list->div_table,
|
||||
&clk_lock);
|
||||
&ctx->lock);
|
||||
else
|
||||
clk = clk_register_divider(NULL, list->name,
|
||||
list->parent_names[0], flags,
|
||||
reg_base + list->muxdiv_offset,
|
||||
ctx->reg_base + list->muxdiv_offset,
|
||||
list->div_shift, list->div_width,
|
||||
list->div_flags, &clk_lock);
|
||||
list->div_flags, &ctx->lock);
|
||||
break;
|
||||
case branch_fraction_divider:
|
||||
clk = rockchip_clk_register_frac_branch(list->name,
|
||||
clk = rockchip_clk_register_frac_branch(ctx, list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
reg_base, list->muxdiv_offset, list->div_flags,
|
||||
ctx->reg_base, list->muxdiv_offset, list->div_flags,
|
||||
list->gate_offset, list->gate_shift,
|
||||
list->gate_flags, flags, list->child,
|
||||
&clk_lock);
|
||||
&ctx->lock);
|
||||
break;
|
||||
case branch_gate:
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
clk = clk_register_gate(NULL, list->name,
|
||||
list->parent_names[0], flags,
|
||||
reg_base + list->gate_offset,
|
||||
list->gate_shift, list->gate_flags, &clk_lock);
|
||||
ctx->reg_base + list->gate_offset,
|
||||
list->gate_shift, list->gate_flags, &ctx->lock);
|
||||
break;
|
||||
case branch_composite:
|
||||
clk = rockchip_clk_register_branch(list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
reg_base, list->muxdiv_offset, list->mux_shift,
|
||||
ctx->reg_base, list->muxdiv_offset, list->mux_shift,
|
||||
list->mux_width, list->mux_flags,
|
||||
list->div_shift, list->div_width,
|
||||
list->div_flags, list->div_table,
|
||||
list->gate_offset, list->gate_shift,
|
||||
list->gate_flags, flags, &clk_lock);
|
||||
list->gate_flags, flags, &ctx->lock);
|
||||
break;
|
||||
case branch_mmc:
|
||||
clk = rockchip_clk_register_mmc(
|
||||
list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
reg_base + list->muxdiv_offset,
|
||||
ctx->reg_base + list->muxdiv_offset,
|
||||
list->div_shift
|
||||
);
|
||||
break;
|
||||
@ -446,16 +478,16 @@ void __init rockchip_clk_register_branches(
|
||||
clk = rockchip_clk_register_inverter(
|
||||
list->name, list->parent_names,
|
||||
list->num_parents,
|
||||
reg_base + list->muxdiv_offset,
|
||||
list->div_shift, list->div_flags, &clk_lock);
|
||||
ctx->reg_base + list->muxdiv_offset,
|
||||
list->div_shift, list->div_flags, &ctx->lock);
|
||||
break;
|
||||
case branch_factor:
|
||||
clk = rockchip_clk_register_factor_branch(
|
||||
list->name, list->parent_names,
|
||||
list->num_parents, reg_base,
|
||||
list->num_parents, ctx->reg_base,
|
||||
list->div_shift, list->div_width,
|
||||
list->gate_offset, list->gate_shift,
|
||||
list->gate_flags, flags, &clk_lock);
|
||||
list->gate_flags, flags, &ctx->lock);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -472,11 +504,12 @@ void __init rockchip_clk_register_branches(
|
||||
continue;
|
||||
}
|
||||
|
||||
rockchip_clk_add_lookup(clk, list->id);
|
||||
rockchip_clk_add_lookup(ctx, clk, list->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init rockchip_clk_register_armclk(unsigned int lookup_id,
|
||||
void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
unsigned int lookup_id,
|
||||
const char *name, const char *const *parent_names,
|
||||
u8 num_parents,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data,
|
||||
@ -486,15 +519,15 @@ void __init rockchip_clk_register_armclk(unsigned int lookup_id,
|
||||
struct clk *clk;
|
||||
|
||||
clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
|
||||
reg_data, rates, nrates, reg_base,
|
||||
&clk_lock);
|
||||
reg_data, rates, nrates, ctx->reg_base,
|
||||
&ctx->lock);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s: %ld\n",
|
||||
__func__, name, PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_add_lookup(clk, lookup_id);
|
||||
rockchip_clk_add_lookup(ctx, clk, lookup_id);
|
||||
}
|
||||
|
||||
void __init rockchip_clk_protect_critical(const char *const clocks[],
|
||||
@ -511,6 +544,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
|
||||
}
|
||||
}
|
||||
|
||||
static void __iomem *rst_base;
|
||||
static unsigned int reg_restart;
|
||||
static void (*cb_restart)(void);
|
||||
static int rockchip_restart_notify(struct notifier_block *this,
|
||||
@ -519,7 +553,7 @@ static int rockchip_restart_notify(struct notifier_block *this,
|
||||
if (cb_restart)
|
||||
cb_restart();
|
||||
|
||||
writel(0xfdb9, reg_base + reg_restart);
|
||||
writel(0xfdb9, rst_base + reg_restart);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
@ -528,10 +562,12 @@ static struct notifier_block rockchip_restart_handler = {
|
||||
.priority = 128,
|
||||
};
|
||||
|
||||
void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
|
||||
void __init rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
||||
unsigned int reg, void (*cb)(void))
|
||||
{
|
||||
int ret;
|
||||
|
||||
rst_base = ctx->reg_base;
|
||||
reg_restart = reg;
|
||||
cb_restart = cb;
|
||||
ret = register_restart_handler(&rockchip_restart_handler);
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#define CLK_ROCKCHIP_CLK_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
struct clk;
|
||||
|
||||
@ -127,6 +128,22 @@ enum rockchip_pll_type {
|
||||
.nb = _nb, \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct rockchip_clk_provider: information about clock provider
|
||||
* @reg_base: virtual address for the register base.
|
||||
* @clk_data: holds clock related data like clk* and number of clocks.
|
||||
* @cru_node: device-node of the clock-provider
|
||||
* @grf: regmap of the general-register-files syscon
|
||||
* @lock: maintains exclusion between callbacks for a given clock-provider.
|
||||
*/
|
||||
struct rockchip_clk_provider {
|
||||
void __iomem *reg_base;
|
||||
struct clk_onecell_data clk_data;
|
||||
struct device_node *cru_node;
|
||||
struct regmap *grf;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct rockchip_pll_rate_table {
|
||||
unsigned long rate;
|
||||
unsigned int nr;
|
||||
@ -194,12 +211,13 @@ struct rockchip_pll_clock {
|
||||
.rate_table = _rtable, \
|
||||
}
|
||||
|
||||
struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
|
||||
struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
|
||||
enum rockchip_pll_type pll_type,
|
||||
const char *name, const char *const *parent_names,
|
||||
u8 num_parents, void __iomem *base, int con_offset,
|
||||
int grf_lock_offset, int lock_shift, int reg_mode,
|
||||
int mode_shift, struct rockchip_pll_rate_table *rate_table,
|
||||
u8 clk_pll_flags, spinlock_t *lock);
|
||||
u8 num_parents, int con_offset, int grf_lock_offset,
|
||||
int lock_shift, int mode_offset, int mode_shift,
|
||||
struct rockchip_pll_rate_table *rate_table,
|
||||
u8 clk_pll_flags);
|
||||
|
||||
struct rockchip_cpuclk_clksel {
|
||||
int reg;
|
||||
@ -558,21 +576,28 @@ struct rockchip_clk_branch {
|
||||
.gate_flags = gf, \
|
||||
}
|
||||
|
||||
void rockchip_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks);
|
||||
struct regmap *rockchip_clk_get_grf(void);
|
||||
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
|
||||
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
|
||||
void __iomem *base, unsigned long nr_clks);
|
||||
void rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx);
|
||||
struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
|
||||
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
struct clk *clk, unsigned int id);
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk);
|
||||
void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
|
||||
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_pll_clock *pll_list,
|
||||
unsigned int nr_pll, int grf_lock_offset);
|
||||
void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
|
||||
void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
unsigned int lookup_id, const char *name,
|
||||
const char *const *parent_names, u8 num_parents,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data,
|
||||
const struct rockchip_cpuclk_rate_table *rates,
|
||||
int nrates);
|
||||
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
|
||||
void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
|
||||
void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
||||
unsigned int reg, void (*cb)(void));
|
||||
|
||||
#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user