Nuvoton WPCM450 FIU SPI flash controller
Merge series from Jonathan Neuschäfer <j.neuschaefer@gmx.net>: This patchset adds DT bindings and a driver for the Flash Interface Unit (FIU), the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The existing NPCM7xx FIU driver is sufficitently incompatible with the WPCM450 FIU that I decided to write a new driver.
This commit is contained in:
Mark Brown
commit
ef3232e3db
@ -0,0 +1,66 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nuvoton WPCM450 Flash Interface Unit (FIU)
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maintainers:
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- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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const: nuvoton,wpcm450-fiu
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reg:
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items:
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- description: FIU registers
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- description: Memory-mapped flash contents
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reg-names:
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items:
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- const: control
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- const: memory
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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nuvoton,shm:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: a phandle to the SHM block (see ../arm/nuvoton,shm.yaml)
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required:
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- compatible
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- reg
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/nuvoton,wpcm450-clk.h>
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spi@c8000000 {
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compatible = "nuvoton,wpcm450-fiu";
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reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "control", "memory";
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clocks = <&clk WPCM450_CLK_FIU>;
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nuvoton,shm = <&shm>;
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flash@0 {
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compatible = "jedec,spi-nor";
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};
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};
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shm: syscon@c8001000 {
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compatible = "nuvoton,wpcm450-shm", "syscon";
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reg = <0xc8001000 0x1000>;
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};
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@ -635,6 +635,17 @@ config SPI_MTK_SNFI
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is implemented as a SPI-MEM controller with pipelined ECC
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capcability.
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config SPI_WPCM_FIU
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tristate "Nuvoton WPCM450 Flash Interface Unit"
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depends on ARCH_NPCM || COMPILE_TEST
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select REGMAP
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help
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This enables support got the Flash Interface Unit SPI controller
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present in the Nuvoton WPCM450 SoC.
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This driver does not support generic SPI. The implementation only
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supports the spi-mem interface.
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config SPI_NPCM_FIU
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tristate "Nuvoton NPCM FLASH Interface Unit"
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depends on ARCH_NPCM || COMPILE_TEST
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@ -83,6 +83,7 @@ obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o
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obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o
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obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
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obj-$(CONFIG_SPI_MXS) += spi-mxs.o
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obj-$(CONFIG_SPI_WPCM_FIU) += spi-wpcm-fiu.o
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obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o
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obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o
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obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o
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508
drivers/spi/spi-wpcm-fiu.c
Normal file
508
drivers/spi/spi-wpcm-fiu.c
Normal file
@ -0,0 +1,508 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2022 Jonathan Neuschäfer
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi-mem.h>
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#define FIU_CFG 0x00
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#define FIU_BURST_BFG 0x01
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#define FIU_RESP_CFG 0x02
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#define FIU_CFBB_PROT 0x03
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#define FIU_FWIN1_LOW 0x04
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#define FIU_FWIN1_HIGH 0x06
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#define FIU_FWIN2_LOW 0x08
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#define FIU_FWIN2_HIGH 0x0a
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#define FIU_FWIN3_LOW 0x0c
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#define FIU_FWIN3_HIGH 0x0e
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#define FIU_PROT_LOCK 0x10
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#define FIU_PROT_CLEAR 0x11
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#define FIU_SPI_FL_CFG 0x14
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#define FIU_UMA_CODE 0x16
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#define FIU_UMA_AB0 0x17
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#define FIU_UMA_AB1 0x18
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#define FIU_UMA_AB2 0x19
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#define FIU_UMA_DB0 0x1a
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#define FIU_UMA_DB1 0x1b
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#define FIU_UMA_DB2 0x1c
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#define FIU_UMA_DB3 0x1d
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#define FIU_UMA_CTS 0x1e
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#define FIU_UMA_ECTS 0x1f
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#define FIU_BURST_CFG_R16 3
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#define FIU_UMA_CTS_D_SIZE(x) (x)
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#define FIU_UMA_CTS_A_SIZE BIT(3)
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#define FIU_UMA_CTS_WR BIT(4)
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#define FIU_UMA_CTS_CS(x) ((x) << 5)
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#define FIU_UMA_CTS_EXEC_DONE BIT(7)
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#define SHM_FLASH_SIZE 0x02
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#define SHM_FLASH_SIZE_STALL_HOST BIT(6)
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/*
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* I observed a typical wait time of 16 iterations for a UMA transfer to
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* finish, so this should be a safe limit.
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*/
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#define UMA_WAIT_ITERATIONS 100
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/* The memory-mapped view of flash is 16 MiB long */
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#define MAX_MEMORY_SIZE_PER_CS (16 << 20)
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#define MAX_MEMORY_SIZE_TOTAL (4 * MAX_MEMORY_SIZE_PER_CS)
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struct wpcm_fiu_spi {
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struct device *dev;
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struct clk *clk;
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void __iomem *regs;
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void __iomem *memory;
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size_t memory_size;
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struct regmap *shm_regmap;
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};
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static void wpcm_fiu_set_opcode(struct wpcm_fiu_spi *fiu, u8 opcode)
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{
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writeb(opcode, fiu->regs + FIU_UMA_CODE);
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}
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static void wpcm_fiu_set_addr(struct wpcm_fiu_spi *fiu, u32 addr)
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{
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writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0);
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writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1);
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writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2);
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}
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static void wpcm_fiu_set_data(struct wpcm_fiu_spi *fiu, const u8 *data, unsigned int nbytes)
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{
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int i;
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for (i = 0; i < nbytes; i++)
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writeb(data[i], fiu->regs + FIU_UMA_DB0 + i);
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}
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static void wpcm_fiu_get_data(struct wpcm_fiu_spi *fiu, u8 *data, unsigned int nbytes)
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{
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int i;
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for (i = 0; i < nbytes; i++)
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data[i] = readb(fiu->regs + FIU_UMA_DB0 + i);
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}
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/*
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* Perform a UMA (User Mode Access) operation, i.e. a software-controlled SPI transfer.
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*/
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static int wpcm_fiu_do_uma(struct wpcm_fiu_spi *fiu, unsigned int cs,
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bool use_addr, bool write, int data_bytes)
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{
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int i = 0;
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u8 cts = FIU_UMA_CTS_EXEC_DONE | FIU_UMA_CTS_CS(cs);
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if (use_addr)
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cts |= FIU_UMA_CTS_A_SIZE;
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if (write)
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cts |= FIU_UMA_CTS_WR;
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cts |= FIU_UMA_CTS_D_SIZE(data_bytes);
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writeb(cts, fiu->regs + FIU_UMA_CTS);
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for (i = 0; i < UMA_WAIT_ITERATIONS; i++)
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if (!(readb(fiu->regs + FIU_UMA_CTS) & FIU_UMA_CTS_EXEC_DONE))
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return 0;
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dev_info(fiu->dev, "UMA transfer has not finished in %d iterations\n", UMA_WAIT_ITERATIONS);
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return -EIO;
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}
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static void wpcm_fiu_ects_assert(struct wpcm_fiu_spi *fiu, unsigned int cs)
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{
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u8 ects = readb(fiu->regs + FIU_UMA_ECTS);
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ects &= ~BIT(cs);
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writeb(ects, fiu->regs + FIU_UMA_ECTS);
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}
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static void wpcm_fiu_ects_deassert(struct wpcm_fiu_spi *fiu, unsigned int cs)
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{
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u8 ects = readb(fiu->regs + FIU_UMA_ECTS);
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ects |= BIT(cs);
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writeb(ects, fiu->regs + FIU_UMA_ECTS);
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}
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struct wpcm_fiu_op_shape {
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bool (*match)(const struct spi_mem_op *op);
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int (*exec)(struct spi_mem *mem, const struct spi_mem_op *op);
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};
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static bool wpcm_fiu_normal_match(const struct spi_mem_op *op)
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{
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// Opcode 0x0b (FAST READ) is treated differently in hardware
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if (op->cmd.opcode == 0x0b)
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return false;
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return (op->addr.nbytes == 0 || op->addr.nbytes == 3) &&
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op->dummy.nbytes == 0 && op->data.nbytes <= 4;
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}
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static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
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int ret;
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wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
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wpcm_fiu_set_addr(fiu, op->addr.val);
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if (op->data.dir == SPI_MEM_DATA_OUT)
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wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
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ret = wpcm_fiu_do_uma(fiu, mem->spi->chip_select, op->addr.nbytes == 3,
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op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
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if (op->data.dir == SPI_MEM_DATA_IN)
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wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
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return ret;
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}
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static bool wpcm_fiu_fast_read_match(const struct spi_mem_op *op)
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{
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return op->cmd.opcode == 0x0b && op->addr.nbytes == 3 &&
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op->dummy.nbytes == 1 &&
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op->data.nbytes >= 1 && op->data.nbytes <= 4 &&
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op->data.dir == SPI_MEM_DATA_IN;
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}
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static int wpcm_fiu_fast_read_exec(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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return -EINVAL;
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}
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/*
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* 4-byte addressing.
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*
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* Flash view: [ C A A A A D D D D]
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* bytes: 13 aa bb cc dd -> 5a a5 f0 0f
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* FIU's view: [ C A A A][ C D D D D]
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* FIU mode: [ read/write][ read ]
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*/
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static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op)
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{
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return op->addr.nbytes == 4 && op->dummy.nbytes == 0 && op->data.nbytes <= 4;
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}
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static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
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int cs = mem->spi->chip_select;
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wpcm_fiu_ects_assert(fiu, cs);
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wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
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wpcm_fiu_set_addr(fiu, op->addr.val >> 8);
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wpcm_fiu_do_uma(fiu, cs, true, false, 0);
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wpcm_fiu_set_opcode(fiu, op->addr.val & 0xff);
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wpcm_fiu_set_addr(fiu, 0);
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if (op->data.dir == SPI_MEM_DATA_OUT)
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wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
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wpcm_fiu_do_uma(fiu, cs, false, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
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wpcm_fiu_ects_deassert(fiu, cs);
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if (op->data.dir == SPI_MEM_DATA_IN)
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wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
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return 0;
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}
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/*
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* RDID (Read Identification) needs special handling because Linux expects to
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* be able to read 6 ID bytes and FIU can only read up to 4 at once.
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*
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* We're lucky in this case, because executing the RDID instruction twice will
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* result in the same result.
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*
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* What we do is as follows (C: write command/opcode byte, D: read data byte,
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* A: write address byte):
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*
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* 1. C D D D
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* 2. C A A A D D D
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*/
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static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op)
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{
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return op->cmd.opcode == 0x9f && op->addr.nbytes == 0 &&
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op->dummy.nbytes == 0 && op->data.nbytes == 6 &&
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op->data.dir == SPI_MEM_DATA_IN;
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}
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static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
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int cs = mem->spi->chip_select;
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/* First transfer */
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wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
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wpcm_fiu_set_addr(fiu, 0);
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wpcm_fiu_do_uma(fiu, cs, false, false, 3);
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wpcm_fiu_get_data(fiu, op->data.buf.in, 3);
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/* Second transfer */
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wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
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wpcm_fiu_set_addr(fiu, 0);
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wpcm_fiu_do_uma(fiu, cs, true, false, 3);
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wpcm_fiu_get_data(fiu, op->data.buf.in + 3, 3);
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return 0;
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}
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/*
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* With some dummy bytes.
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*
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* C A A A X* X D D D D
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* [C A A A D*][C D D D D]
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*/
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static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op)
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{
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// Opcode 0x0b (FAST READ) is treated differently in hardware
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if (op->cmd.opcode == 0x0b)
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return false;
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return (op->addr.nbytes == 0 || op->addr.nbytes == 3) &&
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op->dummy.nbytes >= 1 && op->dummy.nbytes <= 5 &&
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op->data.nbytes <= 4;
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}
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static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
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int cs = mem->spi->chip_select;
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wpcm_fiu_ects_assert(fiu, cs);
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/* First transfer */
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wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
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wpcm_fiu_set_addr(fiu, op->addr.val);
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wpcm_fiu_do_uma(fiu, cs, op->addr.nbytes != 0, true, op->dummy.nbytes - 1);
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/* Second transfer */
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wpcm_fiu_set_opcode(fiu, 0);
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wpcm_fiu_set_addr(fiu, 0);
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wpcm_fiu_do_uma(fiu, cs, false, false, op->data.nbytes);
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wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
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wpcm_fiu_ects_deassert(fiu, cs);
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return 0;
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}
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static const struct wpcm_fiu_op_shape wpcm_fiu_op_shapes[] = {
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{ .match = wpcm_fiu_normal_match, .exec = wpcm_fiu_normal_exec },
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{ .match = wpcm_fiu_fast_read_match, .exec = wpcm_fiu_fast_read_exec },
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{ .match = wpcm_fiu_4ba_match, .exec = wpcm_fiu_4ba_exec },
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{ .match = wpcm_fiu_rdid_match, .exec = wpcm_fiu_rdid_exec },
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{ .match = wpcm_fiu_dummy_match, .exec = wpcm_fiu_dummy_exec },
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};
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static const struct wpcm_fiu_op_shape *wpcm_fiu_find_op_shape(const struct spi_mem_op *op)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(wpcm_fiu_op_shapes); i++) {
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const struct wpcm_fiu_op_shape *shape = &wpcm_fiu_op_shapes[i];
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if (shape->match(op))
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return shape;
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}
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return NULL;
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}
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|
||||
static bool wpcm_fiu_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
||||
{
|
||||
if (!spi_mem_default_supports_op(mem, op))
|
||||
return false;
|
||||
|
||||
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
|
||||
return false;
|
||||
|
||||
if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
|
||||
op->dummy.buswidth > 1 || op->data.buswidth > 1)
|
||||
return false;
|
||||
|
||||
return wpcm_fiu_find_op_shape(op) != NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* In order to ensure the integrity of SPI transfers performed via UMA,
|
||||
* temporarily disable (stall) memory accesses coming from the host CPU.
|
||||
*/
|
||||
static void wpcm_fiu_stall_host(struct wpcm_fiu_spi *fiu, bool stall)
|
||||
{
|
||||
if (fiu->shm_regmap) {
|
||||
int res = regmap_update_bits(fiu->shm_regmap, SHM_FLASH_SIZE,
|
||||
SHM_FLASH_SIZE_STALL_HOST,
|
||||
stall ? SHM_FLASH_SIZE_STALL_HOST : 0);
|
||||
if (res)
|
||||
dev_warn(fiu->dev, "Failed to (un)stall host memory accesses: %d\n", res);
|
||||
}
|
||||
}
|
||||
|
||||
static int wpcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
||||
{
|
||||
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
|
||||
const struct wpcm_fiu_op_shape *shape = wpcm_fiu_find_op_shape(op);
|
||||
|
||||
wpcm_fiu_stall_host(fiu, true);
|
||||
|
||||
if (shape)
|
||||
return shape->exec(mem, op);
|
||||
|
||||
wpcm_fiu_stall_host(fiu, false);
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
|
||||
{
|
||||
if (op->data.nbytes > 4)
|
||||
op->data.nbytes = 4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
|
||||
{
|
||||
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
|
||||
int cs = desc->mem->spi->chip_select;
|
||||
|
||||
if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
|
||||
return -ENOTSUPP;
|
||||
|
||||
/*
|
||||
* Unfortunately, FIU only supports a 16 MiB direct mapping window (per
|
||||
* attached flash chip), but the SPI MEM core doesn't support partial
|
||||
* direct mappings. This means that we can't support direct mapping on
|
||||
* flashes that are bigger than 16 MiB.
|
||||
*/
|
||||
if (desc->info.offset + desc->info.length > MAX_MEMORY_SIZE_PER_CS)
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* Don't read past the memory window */
|
||||
if (cs * MAX_MEMORY_SIZE_PER_CS + desc->info.offset + desc->info.length > fiu->memory_size)
|
||||
return -ENOTSUPP;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf)
|
||||
{
|
||||
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
|
||||
int cs = desc->mem->spi->chip_select;
|
||||
|
||||
if (offs >= MAX_MEMORY_SIZE_PER_CS)
|
||||
return -ENOTSUPP;
|
||||
|
||||
offs += cs * MAX_MEMORY_SIZE_PER_CS;
|
||||
|
||||
if (!fiu->memory || offs >= fiu->memory_size)
|
||||
return -ENOTSUPP;
|
||||
|
||||
len = min_t(size_t, len, fiu->memory_size - offs);
|
||||
memcpy_fromio(buf, fiu->memory + offs, len);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = {
|
||||
.adjust_op_size = wpcm_fiu_adjust_op_size,
|
||||
.supports_op = wpcm_fiu_supports_op,
|
||||
.exec_op = wpcm_fiu_exec_op,
|
||||
.dirmap_create = wpcm_fiu_dirmap_create,
|
||||
.dirmap_read = wpcm_fiu_direct_read,
|
||||
};
|
||||
|
||||
static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu)
|
||||
{
|
||||
/* Configure memory-mapped flash access */
|
||||
writeb(FIU_BURST_CFG_R16, fiu->regs + FIU_BURST_BFG);
|
||||
writeb(MAX_MEMORY_SIZE_TOTAL / (512 << 10), fiu->regs + FIU_CFG);
|
||||
writeb(MAX_MEMORY_SIZE_PER_CS / (512 << 10) | BIT(6), fiu->regs + FIU_SPI_FL_CFG);
|
||||
|
||||
/* Deassert all manually asserted chip selects */
|
||||
writeb(0x0f, fiu->regs + FIU_UMA_ECTS);
|
||||
}
|
||||
|
||||
static int wpcm_fiu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spi_controller *ctrl;
|
||||
struct wpcm_fiu_spi *fiu;
|
||||
struct resource *res;
|
||||
|
||||
ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
|
||||
if (!ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
fiu = spi_controller_get_devdata(ctrl);
|
||||
fiu->dev = dev;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
|
||||
fiu->regs = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(fiu->regs)) {
|
||||
dev_err(dev, "Failed to map registers\n");
|
||||
return PTR_ERR(fiu->regs);
|
||||
}
|
||||
|
||||
fiu->clk = devm_clk_get_enabled(dev, NULL);
|
||||
if (IS_ERR(fiu->clk))
|
||||
return PTR_ERR(fiu->clk);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
|
||||
fiu->memory = devm_ioremap_resource(dev, res);
|
||||
fiu->memory_size = min_t(size_t, resource_size(res), MAX_MEMORY_SIZE_TOTAL);
|
||||
if (IS_ERR(fiu->memory)) {
|
||||
dev_err(dev, "Failed to map flash memory window\n");
|
||||
return PTR_ERR(fiu->memory);
|
||||
}
|
||||
|
||||
fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm");
|
||||
|
||||
wpcm_fiu_hw_init(fiu);
|
||||
|
||||
ctrl->bus_num = -1;
|
||||
ctrl->mem_ops = &wpcm_fiu_mem_ops;
|
||||
ctrl->num_chipselect = 4;
|
||||
ctrl->dev.of_node = dev->of_node;
|
||||
|
||||
/*
|
||||
* The FIU doesn't include a clock divider, the clock is entirely
|
||||
* determined by the AHB3 bus clock.
|
||||
*/
|
||||
ctrl->min_speed_hz = clk_get_rate(fiu->clk);
|
||||
ctrl->max_speed_hz = clk_get_rate(fiu->clk);
|
||||
|
||||
return devm_spi_register_controller(dev, ctrl);
|
||||
}
|
||||
|
||||
static const struct of_device_id wpcm_fiu_dt_ids[] = {
|
||||
{ .compatible = "nuvoton,wpcm450-fiu", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, wpcm_fiu_dt_ids);
|
||||
|
||||
static struct platform_driver wpcm_fiu_driver = {
|
||||
.driver = {
|
||||
.name = "wpcm450-fiu",
|
||||
.bus = &platform_bus_type,
|
||||
.of_match_table = wpcm_fiu_dt_ids,
|
||||
},
|
||||
.probe = wpcm_fiu_probe,
|
||||
};
|
||||
module_platform_driver(wpcm_fiu_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver");
|
||||
MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user