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drm/i915: add WRPLL divider programming bits

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Those are used to program the WRPLL dividers correctly for each gives
frequency.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Eugeni Dodonov 2012-04-13 17:08:38 -03:00 committed by Daniel Vetter
parent dc04a61a05
commit ef4d084fae
1 changed files with 4 additions and 0 deletions

4
drivers/gpu/drm/i915/i915_reg.h

@ -4191,6 +4191,10 @@
#define WRPLL_PLL_SELECT_SSC (0x01<<28)
#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
/* WRPLL divider programming */
#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
#define WRPLL_DIVIDER_POST(x) ((x)<<8)
#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
/* Port clock selection */
#define PORT_CLK_SEL_A 0x46100