staging:iio:cdc:ad7150: More consistent register and field naming
Add _REG postfix to register addresses to avoid confusion with fields. Also add additional field defines and use throughout the driver in place of magic numbers. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210314181511.531414-14-jic23@kernel.org
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Jonathan Cameron
parent
9623caea2c
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ef71bd9c85
@ -21,37 +21,38 @@
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* AD7150 registers definition
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*/
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#define AD7150_STATUS 0
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#define AD7150_STATUS_OUT1 BIT(3)
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#define AD7150_STATUS_OUT2 BIT(5)
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#define AD7150_CH1_DATA_HIGH 1
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#define AD7150_CH2_DATA_HIGH 3
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#define AD7150_CH1_AVG_HIGH 5
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#define AD7150_CH2_AVG_HIGH 7
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#define AD7150_CH1_SENSITIVITY 9
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#define AD7150_CH1_THR_HOLD_H 9
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#define AD7150_CH1_TIMEOUT 10
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#define AD7150_CH1_SETUP 11
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#define AD7150_CH2_SENSITIVITY 12
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#define AD7150_CH2_THR_HOLD_H 12
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#define AD7150_CH2_TIMEOUT 13
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#define AD7150_CH2_SETUP 14
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#define AD7150_CFG 15
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#define AD7150_CFG_FIX BIT(7)
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#define AD7150_PD_TIMER 16
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#define AD7150_CH1_CAPDAC 17
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#define AD7150_CH2_CAPDAC 18
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#define AD7150_SN3 19
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#define AD7150_SN2 20
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#define AD7150_SN1 21
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#define AD7150_SN0 22
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#define AD7150_ID 23
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/* AD7150 masks */
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#define AD7150_THRESHTYPE_MSK GENMASK(6, 5)
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#define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)
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#define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)
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#define AD7150_STATUS_REG 0
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#define AD7150_STATUS_OUT1 BIT(3)
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#define AD7150_STATUS_OUT2 BIT(5)
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#define AD7150_CH1_DATA_HIGH_REG 1
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#define AD7150_CH2_DATA_HIGH_REG 3
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#define AD7150_CH1_AVG_HIGH_REG 5
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#define AD7150_CH2_AVG_HIGH_REG 7
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#define AD7150_CH1_SENSITIVITY_REG 9
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#define AD7150_CH1_THR_HOLD_H_REG 9
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#define AD7150_CH1_TIMEOUT_REG 10
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#define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)
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#define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)
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#define AD7150_CH1_SETUP_REG 11
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#define AD7150_CH2_SENSITIVITY_REG 12
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#define AD7150_CH2_THR_HOLD_H_REG 12
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#define AD7150_CH2_TIMEOUT_REG 13
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#define AD7150_CH2_SETUP_REG 14
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#define AD7150_CFG_REG 15
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#define AD7150_CFG_FIX BIT(7)
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#define AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5)
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#define AD7150_CFG_TT_NEG 0x0
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#define AD7150_CFG_TT_POS 0x1
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#define AD7150_CFG_TT_IN_WINDOW 0x2
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#define AD7150_CFG_TT_OUT_WINDOW 0x3
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#define AD7150_PD_TIMER_REG 16
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#define AD7150_CH1_CAPDAC_REG 17
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#define AD7150_CH2_CAPDAC_REG 18
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#define AD7150_SN3_REG 19
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#define AD7150_SN2_REG 20
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#define AD7150_SN1_REG 21
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#define AD7150_SN0_REG 22
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#define AD7150_ID_REG 23
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enum {
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AD7150,
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@ -93,12 +94,12 @@ struct ad7150_chip_info {
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*/
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static const u8 ad7150_addresses[][6] = {
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{ AD7150_CH1_DATA_HIGH, AD7150_CH1_AVG_HIGH,
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AD7150_CH1_SETUP, AD7150_CH1_THR_HOLD_H,
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AD7150_CH1_SENSITIVITY, AD7150_CH1_TIMEOUT },
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{ AD7150_CH2_DATA_HIGH, AD7150_CH2_AVG_HIGH,
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AD7150_CH2_SETUP, AD7150_CH2_THR_HOLD_H,
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AD7150_CH2_SENSITIVITY, AD7150_CH2_TIMEOUT },
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{ AD7150_CH1_DATA_HIGH_REG, AD7150_CH1_AVG_HIGH_REG,
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AD7150_CH1_SETUP_REG, AD7150_CH1_THR_HOLD_H_REG,
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AD7150_CH1_SENSITIVITY_REG, AD7150_CH1_TIMEOUT_REG },
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{ AD7150_CH2_DATA_HIGH_REG, AD7150_CH2_AVG_HIGH_REG,
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AD7150_CH2_SETUP_REG, AD7150_CH2_THR_HOLD_H_REG,
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AD7150_CH2_SENSITIVITY_REG, AD7150_CH2_TIMEOUT_REG },
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};
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static int ad7150_read_raw(struct iio_dev *indio_dev,
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@ -147,11 +148,11 @@ static int ad7150_read_event_config(struct iio_dev *indio_dev,
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bool thrfixed;
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struct ad7150_chip_info *chip = iio_priv(indio_dev);
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ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG);
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ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
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if (ret < 0)
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return ret;
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threshtype = FIELD_GET(AD7150_THRESHTYPE_MSK, ret);
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threshtype = FIELD_GET(AD7150_CFG_THRESHTYPE_MSK, ret);
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/*check if threshold mode is fixed or adaptive*/
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thrfixed = FIELD_GET(AD7150_CFG_FIX, ret);
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@ -159,12 +160,12 @@ static int ad7150_read_event_config(struct iio_dev *indio_dev,
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switch (type) {
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case IIO_EV_TYPE_THRESH_ADAPTIVE:
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if (dir == IIO_EV_DIR_RISING)
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return !thrfixed && (threshtype == 0x1);
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return !thrfixed && (threshtype == 0x0);
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return !thrfixed && (threshtype == AD7150_CFG_TT_POS);
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return !thrfixed && (threshtype == AD7150_CFG_TT_NEG);
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case IIO_EV_TYPE_THRESH:
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if (dir == IIO_EV_DIR_RISING)
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return thrfixed && (threshtype == 0x1);
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return thrfixed && (threshtype == 0x0);
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return thrfixed && (threshtype == AD7150_CFG_TT_POS);
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return thrfixed && (threshtype == AD7150_CFG_TT_NEG);
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default:
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break;
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}
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@ -226,7 +227,7 @@ static int ad7150_write_event_config(struct iio_dev *indio_dev,
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enum iio_event_type type,
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enum iio_event_direction dir, int state)
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{
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u8 thresh_type, cfg, adaptive;
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u8 thresh_type, cfg, fixed;
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int ret;
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struct ad7150_chip_info *chip = iio_priv(indio_dev);
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int rising = (dir == IIO_EV_DIR_RISING);
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@ -261,35 +262,27 @@ static int ad7150_write_event_config(struct iio_dev *indio_dev,
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disable_irq(chip->interrupts[0]);
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disable_irq(chip->interrupts[1]);
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ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG);
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ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
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if (ret < 0)
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goto error_ret;
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cfg = ret & ~((0x03 << 5) | BIT(7));
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cfg = ret & ~(AD7150_CFG_THRESHTYPE_MSK | AD7150_CFG_FIX);
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switch (type) {
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case IIO_EV_TYPE_THRESH_ADAPTIVE:
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adaptive = 1;
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if (rising)
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thresh_type = 0x1;
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else
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thresh_type = 0x0;
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break;
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case IIO_EV_TYPE_THRESH:
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adaptive = 0;
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if (rising)
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thresh_type = 0x1;
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else
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thresh_type = 0x0;
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break;
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default:
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ret = -EINVAL;
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goto error_ret;
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}
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if (type == IIO_EV_TYPE_THRESH_ADAPTIVE)
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fixed = 0;
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else
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fixed = 1;
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cfg |= (!adaptive << 7) | (thresh_type << 5);
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if (rising)
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thresh_type = AD7150_CFG_TT_POS;
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else
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thresh_type = AD7150_CFG_TT_NEG;
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ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG, cfg);
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cfg |= FIELD_PREP(AD7150_CFG_FIX, fixed) |
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FIELD_PREP(AD7150_CFG_THRESHTYPE_MSK, thresh_type);
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ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG_REG,
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cfg);
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if (ret < 0)
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goto error_ret;
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@ -480,7 +473,7 @@ static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask,
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s64 timestamp = iio_get_time_ns(indio_dev);
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int int_status;
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int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS);
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int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS_REG);
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if (int_status < 0)
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return IRQ_HANDLED;
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