perf vendor events: Update Intel broadwellde
Update to v7, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwellde files into perf and update mapfile.csv. Tested on a non-broadwellde with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sedat Dilek <sedat.dilek@gmail.com> Cc: Stephane Eranian <eranian@google.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Link: http://lore.kernel.org/lkml/20220727220832.2865794-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
Arnaldo Carvalho de Melo
parent
1775634ea4
commit
ef908a1925
@ -47,7 +47,7 @@
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"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
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"MetricGroup": "TopdownL1",
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"MetricName": "Retiring",
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"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided."
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"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. "
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},
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{
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"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
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@ -130,43 +130,25 @@
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"MetricName": "FLOPc_SMT"
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},
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{
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"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",
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"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
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"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
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"MetricGroup": "Cor;Flops;HPC",
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"MetricName": "FP_Arith_Utilization",
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"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."
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"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
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},
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{
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"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",
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"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). SMT version; use when SMT is enabled and measuring per logical CPU.",
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"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
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"MetricGroup": "Cor;Flops;HPC_SMT",
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"MetricName": "FP_Arith_Utilization_SMT",
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"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."
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"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common). SMT version; use when SMT is enabled and measuring per logical CPU."
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},
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{
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
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"MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
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"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
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"MetricName": "ILP"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts",
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"MetricName": "Branch_Misprediction_Cost"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts_SMT",
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"MetricName": "Branch_Misprediction_Cost_SMT"
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},
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{
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"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
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"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BadSpec;BrMispredicts",
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"MetricName": "IpMispredict"
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},
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{
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"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
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"MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
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@ -204,7 +186,7 @@
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"MetricName": "IpTB"
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},
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{
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"BriefDescription": "Branch instructions per taken branch.",
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"BriefDescription": "Branch instructions per taken branch. ",
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"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
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"MetricGroup": "Branches;Fed;PGO",
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"MetricName": "BpTkBranch"
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@ -256,18 +238,47 @@
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"MetricGroup": "Summary;TmaL1",
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"MetricName": "Instructions"
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},
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{
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"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
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"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
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"MetricGroup": "Pipeline;Ret",
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"MetricName": "Retire"
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},
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{
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"BriefDescription": "",
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"MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
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"MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
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"MetricName": "Execute"
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},
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{
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"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
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"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
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"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
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"MetricGroup": "DSB;Fed;FetchBW",
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"MetricName": "DSB_Coverage"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
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"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
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"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BadSpec;BrMispredicts",
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"MetricName": "IpMispredict"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts",
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"MetricName": "Branch_Misprediction_Cost"
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts_SMT",
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"MetricName": "Branch_Misprediction_Cost_SMT"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
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"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
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"MetricGroup": "Mem;MemoryBound;MemoryLat",
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"MetricName": "Load_Miss_Real_Latency",
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"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
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"MetricName": "Load_Miss_Real_Latency"
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},
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{
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"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
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@ -275,24 +286,6 @@
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"MetricGroup": "Mem;MemoryBound;MemoryBW",
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"MetricName": "MLP"
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},
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{
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"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW"
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},
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{
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"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
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"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
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@ -306,13 +299,13 @@
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"MetricName": "L2MPKI"
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},
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{
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"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
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"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
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"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
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"MetricGroup": "Mem;CacheMisses;Offcore",
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"MetricName": "L2MPKI_All"
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},
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{
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"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)",
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"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
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"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
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"MetricGroup": "Mem;CacheMisses",
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"MetricName": "L2MPKI_Load"
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@ -348,6 +341,48 @@
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"MetricGroup": "Mem;MemoryTLB_SMT",
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"MetricName": "Page_Walks_Utilization_SMT"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
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"MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L1D_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
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"MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L2_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)",
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"MetricGroup": "Mem;MemoryBW",
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"MetricName": "L3_Cache_Fill_BW_1T"
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},
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{
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"BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
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"MetricExpr": "0",
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"MetricGroup": "Mem;MemoryBW;Offcore",
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"MetricName": "L3_Cache_Access_BW_1T"
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},
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{
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"BriefDescription": "Average CPU Utilization",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
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@ -364,7 +399,8 @@
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"BriefDescription": "Giga Floating Point Operations Per Second",
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"MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
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"MetricGroup": "Cor;Flops;HPC",
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"MetricName": "GFLOPs"
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"MetricName": "GFLOPs",
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"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
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},
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{
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"BriefDescription": "Average Frequency Utilization relative nominal frequency",
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@ -806,4 +806,4 @@
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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}
|
||||
]
|
||||
]
|
||||
|
||||
@ -190,4 +190,4 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x3"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
@ -292,4 +292,4 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
@ -429,4 +429,4 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x40"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
@ -41,4 +41,4 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
@ -1378,4 +1378,4 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,91 +1,511 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "PCU clock ticks. Use to get percentages of PCU cycles events",
|
||||
"BriefDescription": "pclk Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UNC_P_CLOCKTICKS",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details",
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
|
||||
"Filter": "occ_sel=1",
|
||||
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "power_state_occupancy.cores_c0 %",
|
||||
"EventCode": "0x60",
|
||||
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details",
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
|
||||
"Filter": "occ_sel=2",
|
||||
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "power_state_occupancy.cores_c3 %",
|
||||
"EventCode": "0x6A",
|
||||
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events ",
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
|
||||
"Filter": "occ_sel=3",
|
||||
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "power_state_occupancy.cores_c6 %",
|
||||
"EventCode": "0x6B",
|
||||
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip",
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xA",
|
||||
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
|
||||
"MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "prochot_external_cycles %",
|
||||
"EventCode": "0x6C",
|
||||
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles when temperature is the upper limit on frequency",
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x6D",
|
||||
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x6E",
|
||||
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x6F",
|
||||
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x70",
|
||||
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x71",
|
||||
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x61",
|
||||
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x62",
|
||||
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x63",
|
||||
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x64",
|
||||
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x65",
|
||||
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x66",
|
||||
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x67",
|
||||
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x68",
|
||||
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x69",
|
||||
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x30",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE0",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x31",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE1",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x3A",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE10",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x3B",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE11",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x3C",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE12",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x3D",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE13",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x3E",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE14",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x3F",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE15",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x40",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE16",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x41",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE17",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x32",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE2",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x33",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE3",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x34",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE4",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x35",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE5",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x36",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE6",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x37",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE7",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x38",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE8",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Core C State Demotions",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x39",
|
||||
"EventName": "UNC_P_DEMOTIONS_CORE9",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x4",
|
||||
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
|
||||
"MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "freq_max_limit_thermal_cycles %",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles when the OS is the upper limit on frequency",
|
||||
"BriefDescription": "OS Strongest Upper Limit Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x6",
|
||||
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
|
||||
"MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "freq_max_os_cycles %",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles when power is the upper limit on frequency",
|
||||
"BriefDescription": "Power Strongest Upper Limit Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x5",
|
||||
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
|
||||
"MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "freq_max_power_cycles %",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Counts the number of cycles when current is the upper limit on frequency",
|
||||
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x73",
|
||||
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles spent changing Frequency",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x74",
|
||||
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
|
||||
"MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.",
|
||||
"MetricName": "freq_trans_cycles %",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Memory Phase Shedding Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2F",
|
||||
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Package C State Residency - C0",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Package C State Residency - C1E",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x4E",
|
||||
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Package C State Residency - C2E",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2B",
|
||||
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Package C State Residency - C3",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2C",
|
||||
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Package C State Residency - C6",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2D",
|
||||
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Package C7 State Residency",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x2E",
|
||||
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of cores in C-State; C0 and C1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of cores in C-State; C3",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Number of cores in C-State; C6 and C7",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x80",
|
||||
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "External Prochot",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0xA",
|
||||
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Internal Prochot",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x9",
|
||||
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Total Core C State Transition Cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x72",
|
||||
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x79",
|
||||
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
|
||||
"PerPkg": "1",
|
||||
"PublicDescription": "Ring GV with same final and initial frequency",
|
||||
"Unit": "PCU"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "VR Hot",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventCode": "0x42",
|
||||
"EventName": "UNC_P_VR_HOT_CYCLES",
|
||||
"PerPkg": "1",
|
||||
"Unit": "PCU"
|
||||
}
|
||||
|
||||
@ -385,4 +385,4 @@
|
||||
"SampleAfterValue": "100007",
|
||||
"UMask": "0x20"
|
||||
}
|
||||
]
|
||||
]
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Family-model,Version,Filename,EventType
|
||||
GenuineIntel-6-56,v5,broadwellde,core
|
||||
GenuineIntel-6-(3D|47),v26,broadwell,core
|
||||
GenuineIntel-6-56,v23,broadwellde,core
|
||||
GenuineIntel-6-4F,v19,broadwellx,core
|
||||
GenuineIntel-6-1C,v4,bonnell,core
|
||||
GenuineIntel-6-26,v4,bonnell,core
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user