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riscv: dts: microchip: hook up the mpfs' l2cache

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The initial PolarFire SoC devicetree must have been forked off from
the fu540 one prior to the addition of l2cache controller support being
added there. When the controller node was added to mpfs.dtsi, it was
not hooked up to the CPUs & thus sysfs reports an incorrect cache
configuration. Hook it up.

Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2022-06-29 21:07:33 +01:00
parent 5e757deddd
commit efa310ba00
1 changed files with 4 additions and 0 deletions
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4
arch/riscv/boot/dts/microchip/mpfs.dtsi
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@ -50,6 +50,7 @@
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>; clocks = <&clkcfg CLK_CPU>;
tlb-split; tlb-split;
next-level-cache = <&cctrllr>;
status = "okay"; status = "okay";
cpu1_intc: interrupt-controller { cpu1_intc: interrupt-controller {
@ -77,6 +78,7 @@
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>; clocks = <&clkcfg CLK_CPU>;
tlb-split; tlb-split;
next-level-cache = <&cctrllr>;
status = "okay"; status = "okay";
cpu2_intc: interrupt-controller { cpu2_intc: interrupt-controller {
@ -104,6 +106,7 @@
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>; clocks = <&clkcfg CLK_CPU>;
tlb-split; tlb-split;
next-level-cache = <&cctrllr>;
status = "okay"; status = "okay";
cpu3_intc: interrupt-controller { cpu3_intc: interrupt-controller {
@ -131,6 +134,7 @@
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>; clocks = <&clkcfg CLK_CPU>;
tlb-split; tlb-split;
next-level-cache = <&cctrllr>;
status = "okay"; status = "okay";
cpu4_intc: interrupt-controller { cpu4_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;