ixgbe: convert rings from q_vector bit indexed array to linked list
This change converts the current bit array into a linked list so that the q_vectors can simply go through ring by ring and locate each ring needing to be cleaned. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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30065e63d8
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@ -209,6 +209,7 @@ enum ixbge_ring_state_t {
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#define clear_ring_rsc_enabled(ring) \
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clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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struct ixgbe_ring {
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struct ixgbe_ring *next; /* pointer to next ring in q_vector */
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void *desc; /* descriptor ring memory */
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struct device *dev; /* device for DMA mapping */
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struct net_device *netdev; /* netdev ring belongs to */
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@ -277,11 +278,7 @@ struct ixgbe_ring_feature {
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} ____cacheline_internodealigned_in_smp;
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struct ixgbe_ring_container {
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#if MAX_RX_QUEUES > MAX_TX_QUEUES
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DECLARE_BITMAP(idx, MAX_RX_QUEUES);
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#else
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DECLARE_BITMAP(idx, MAX_TX_QUEUES);
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#endif
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struct ixgbe_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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@ -974,26 +974,17 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
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static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
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{
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *ring;
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int cpu = get_cpu();
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long r_idx;
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int i;
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if (q_vector->cpu == cpu)
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goto out_no_update;
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r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
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for (i = 0; i < q_vector->tx.count; i++) {
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ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
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r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
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r_idx + 1);
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}
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for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
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ixgbe_update_tx_dca(adapter, ring, cpu);
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r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
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for (i = 0; i < q_vector->rx.count; i++) {
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ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
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r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
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r_idx + 1);
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}
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for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
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ixgbe_update_rx_dca(adapter, ring, cpu);
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q_vector->cpu = cpu;
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out_no_update:
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@ -1546,7 +1537,7 @@ static int ixgbe_clean_rxonly(struct napi_struct *, int);
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static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
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{
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struct ixgbe_q_vector *q_vector;
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int i, q_vectors, v_idx, r_idx;
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int q_vectors, v_idx;
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u32 mask;
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q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
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@ -1556,33 +1547,19 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
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* corresponding register.
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*/
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for (v_idx = 0; v_idx < q_vectors; v_idx++) {
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struct ixgbe_ring *ring;
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q_vector = adapter->q_vector[v_idx];
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/* XXX for_each_set_bit(...) */
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r_idx = find_first_bit(q_vector->rx.idx,
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adapter->num_rx_queues);
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for (i = 0; i < q_vector->rx.count; i++) {
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u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
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ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
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r_idx = find_next_bit(q_vector->rx.idx,
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adapter->num_rx_queues,
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r_idx + 1);
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}
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r_idx = find_first_bit(q_vector->tx.idx,
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adapter->num_tx_queues);
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for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
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ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
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for (i = 0; i < q_vector->tx.count; i++) {
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u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
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ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
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r_idx = find_next_bit(q_vector->tx.idx,
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adapter->num_tx_queues,
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r_idx + 1);
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}
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for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
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ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
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if (q_vector->tx.count && !q_vector->rx.count)
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if (q_vector->tx.ring && !q_vector->rx.ring)
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/* tx only */
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q_vector->eitr = adapter->tx_eitr_param;
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else if (q_vector->rx.count)
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else if (q_vector->rx.ring)
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/* rx or mixed */
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q_vector->eitr = adapter->rx_eitr_param;
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@ -2006,20 +1983,10 @@ static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
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static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
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{
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struct ixgbe_q_vector *q_vector = data;
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *tx_ring;
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int i, r_idx;
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if (!q_vector->tx.count)
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return IRQ_HANDLED;
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r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
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for (i = 0; i < q_vector->tx.count; i++) {
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tx_ring = adapter->tx_ring[r_idx];
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r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
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r_idx + 1);
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}
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/* EIAM disabled interrupts (on this vector) for us */
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napi_schedule(&q_vector->napi);
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@ -2034,22 +2001,6 @@ static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
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static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
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{
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struct ixgbe_q_vector *q_vector = data;
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *rx_ring;
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int r_idx;
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int i;
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#ifdef CONFIG_IXGBE_DCA
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if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
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ixgbe_update_dca(q_vector);
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#endif
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r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
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for (i = 0; i < q_vector->rx.count; i++) {
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rx_ring = adapter->rx_ring[r_idx];
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r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
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r_idx + 1);
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}
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if (!q_vector->rx.count)
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return IRQ_HANDLED;
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@ -2063,28 +2014,10 @@ static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
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static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
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{
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struct ixgbe_q_vector *q_vector = data;
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *ring;
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int r_idx;
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int i;
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if (!q_vector->tx.count && !q_vector->rx.count)
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return IRQ_HANDLED;
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r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
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for (i = 0; i < q_vector->tx.count; i++) {
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ring = adapter->tx_ring[r_idx];
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r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
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r_idx + 1);
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}
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r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
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for (i = 0; i < q_vector->rx.count; i++) {
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ring = adapter->rx_ring[r_idx];
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r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
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r_idx + 1);
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}
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/* EIAM disabled interrupts (on this vector) for us */
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napi_schedule(&q_vector->napi);
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@ -2104,19 +2037,14 @@ static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
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struct ixgbe_q_vector *q_vector =
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container_of(napi, struct ixgbe_q_vector, napi);
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *rx_ring = NULL;
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int work_done = 0;
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long r_idx;
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#ifdef CONFIG_IXGBE_DCA
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if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
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ixgbe_update_dca(q_vector);
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#endif
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r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
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rx_ring = adapter->rx_ring[r_idx];
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ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
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ixgbe_clean_rx_irq(q_vector, q_vector->rx.ring, &work_done, budget);
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/* If all Rx work done, exit the polling mode */
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if (work_done < budget) {
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@ -2144,38 +2072,29 @@ static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
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struct ixgbe_q_vector *q_vector =
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container_of(napi, struct ixgbe_q_vector, napi);
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *ring = NULL;
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int work_done = 0, i;
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long r_idx;
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bool tx_clean_complete = true;
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struct ixgbe_ring *ring;
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int work_done = 0;
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bool clean_complete = true;
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#ifdef CONFIG_IXGBE_DCA
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if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
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ixgbe_update_dca(q_vector);
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#endif
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r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
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for (i = 0; i < q_vector->tx.count; i++) {
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ring = adapter->tx_ring[r_idx];
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tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
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r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
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r_idx + 1);
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}
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for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
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clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
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/* attempt to distribute budget to each queue fairly, but don't allow
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* the budget to go below 1 because we'll exit polling */
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budget /= (q_vector->rx.count ?: 1);
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budget = max(budget, 1);
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r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
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for (i = 0; i < q_vector->rx.count; i++) {
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ring = adapter->rx_ring[r_idx];
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ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
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r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
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r_idx + 1);
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}
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r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
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ring = adapter->rx_ring[r_idx];
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for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
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ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
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if (!clean_complete)
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work_done = budget;
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/* If all Rx work done, exit the polling mode */
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if (work_done < budget) {
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napi_complete(napi);
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@ -2203,32 +2122,23 @@ static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
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struct ixgbe_q_vector *q_vector =
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container_of(napi, struct ixgbe_q_vector, napi);
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struct ixgbe_adapter *adapter = q_vector->adapter;
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struct ixgbe_ring *tx_ring = NULL;
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int work_done = 0;
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long r_idx;
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#ifdef CONFIG_IXGBE_DCA
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if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
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ixgbe_update_dca(q_vector);
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#endif
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r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
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tx_ring = adapter->tx_ring[r_idx];
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if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
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work_done = budget;
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if (!ixgbe_clean_tx_irq(q_vector, q_vector->tx.ring))
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return budget;
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/* If all Tx work done, exit the polling mode */
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if (work_done < budget) {
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napi_complete(napi);
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if (adapter->tx_itr_setting & 1)
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ixgbe_set_itr(q_vector);
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if (!test_bit(__IXGBE_DOWN, &adapter->state))
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ixgbe_irq_enable_queues(adapter,
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((u64)1 << q_vector->v_idx));
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}
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napi_complete(napi);
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if (adapter->tx_itr_setting & 1)
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ixgbe_set_itr(q_vector);
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if (!test_bit(__IXGBE_DOWN, &adapter->state))
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ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
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return work_done;
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return 0;
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}
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static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
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@ -2237,9 +2147,10 @@ static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
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struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
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struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
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set_bit(r_idx, q_vector->rx.idx);
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q_vector->rx.count++;
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rx_ring->q_vector = q_vector;
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rx_ring->next = q_vector->rx.ring;
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q_vector->rx.ring = rx_ring;
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q_vector->rx.count++;
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}
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static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
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@ -2248,9 +2159,10 @@ static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
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struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
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struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
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set_bit(t_idx, q_vector->tx.idx);
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q_vector->tx.count++;
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tx_ring->q_vector = q_vector;
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tx_ring->next = q_vector->tx.ring;
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q_vector->tx.ring = tx_ring;
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q_vector->tx.count++;
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q_vector->tx.work_limit = a->tx_work_limit;
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}
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@ -2508,14 +2420,26 @@ static irqreturn_t ixgbe_intr(int irq, void *data)
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static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
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{
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int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
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int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
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int i;
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/* legacy and MSI only use one vector */
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if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
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q_vectors = 1;
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for (i = 0; i < adapter->num_rx_queues; i++) {
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adapter->rx_ring[i]->q_vector = NULL;
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adapter->rx_ring[i]->next = NULL;
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}
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for (i = 0; i < adapter->num_tx_queues; i++) {
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adapter->tx_ring[i]->q_vector = NULL;
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adapter->tx_ring[i]->next = NULL;
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}
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for (i = 0; i < q_vectors; i++) {
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struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
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bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
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bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
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q_vector->rx.count = 0;
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q_vector->tx.count = 0;
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memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
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memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
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}
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}
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@ -5923,7 +5847,7 @@ static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
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/* get one bit for every active tx/rx interrupt vector */
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for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
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struct ixgbe_q_vector *qv = adapter->q_vector[i];
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if (qv->rx.count || qv->tx.count)
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if (qv->rx.ring || qv->tx.ring)
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eics |= ((u64)1 << i);
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}
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}
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