platform/x86: amd: pmc: provide user message where s0ix is not supported
Some platforms do not support hardware backed s0i3 transitions. When such CPUs are detected, provide a warning message to the user. Suggested-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230412111500.2602529-1-Shyam-sundar.S-k@amd.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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@ -94,6 +94,7 @@
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#define AMD_CPU_ID_YC 0x14B5
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#define AMD_CPU_ID_CB 0x14D8
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#define AMD_CPU_ID_PS 0x14E8
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#define AMD_CPU_ID_SP 0x14A4
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#define PMC_MSG_DELAY_MIN_US 50
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#define RESPONSE_REGISTER_LOOP_MAX 20000
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@ -886,6 +887,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
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{ }
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};
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@ -964,6 +966,13 @@ static int amd_pmc_probe(struct platform_device *pdev)
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}
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dev->cpu_id = rdev->device;
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if (dev->cpu_id == AMD_CPU_ID_SP) {
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dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
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err = -ENODEV;
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goto err_pci_dev_put;
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}
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dev->rdev = rdev;
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err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
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if (err) {
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