[ARM] nommu: manage the CP15 things
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:
Related operation Safe condition
a. any CP15 access !CPU_CP15
b. alignment trap CPU_CP15_MMU
c. D-cache(C-bit) CPU_CP15
d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
CPU_ARM720 || CPU_ARM740 ||
CPU_XSCALE || CPU_XSC3 )
e. alternate vector CPU_CP15 && !CPU_ARM740
f. TTB CPU_CP15_MMU
g. Domain CPU_CP15_MMU
h. FSR/FAR CPU_CP15_MMU
For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Hyok S. Choi
Russell King
parent
fefdaa06cc
commit
f12d0d7c77
@ -621,6 +621,7 @@ config LEDS_CPU
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config ALIGNMENT_TRAP
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bool
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depends on CPU_CP15_MMU
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default y if !ARCH_EBSA110
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help
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ARM processors can not fetch/store information which is not
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@ -852,7 +853,7 @@ source "drivers/base/Kconfig"
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source "drivers/connector/Kconfig"
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if ALIGNMENT_TRAP
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if ALIGNMENT_TRAP || !CPU_CP15_MMU
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source "drivers/mtd/Kconfig"
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endif
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@ -25,6 +25,14 @@ config FLASH_SIZE
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hex 'FLASH Size' if SET_MEM_PARAM
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default 0x00400000
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config PROCESSOR_ID
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hex
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default 0x00007700
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depends on !CPU_CP15
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help
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If processor has no CP15 register, this processor ID is
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used instead of the auto-probing which utilizes the register.
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config REMAP_VECTORS_TO_RAM
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bool 'Install vectors to the begining of RAM' if DRAM_BASE
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depends on DRAM_BASE
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@ -51,7 +51,11 @@ OBJS += head-at91rm9200.o
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endif
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ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
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ifeq ($(CONFIG_CPU_CP15),y)
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OBJS += big-endian.o
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else
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# The endian should be set by h/w design.
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endif
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endif
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#
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@ -82,9 +82,11 @@
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kphex r6, 8 /* processor id */
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kputc #':'
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kphex r7, 8 /* architecture id */
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#ifdef CONFIG_CPU_CP15
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kputc #':'
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mrc p15, 0, r0, c1, c0
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kphex r0, 8 /* control reg */
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#endif
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kputc #'\n'
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kphex r5, 8 /* decompressed kernel start */
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kputc #'-'
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@ -507,7 +509,11 @@ call_kernel: bl cache_clean_flush
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*/
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call_cache_fn: adr r12, proc_types
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#ifdef CONFIG_CPU_CP15
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mrc p15, 0, r6, c0, c0 @ get processor ID
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#else
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ldr r6, =CONFIG_PROCESSOR_ID
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#endif
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1: ldr r1, [r12, #0] @ get value
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ldr r2, [r12, #4] @ get mask
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eor r1, r1, r6 @ (real ^ match)
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@ -9,7 +9,6 @@
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* published by the Free Software Foundation.
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*
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* Common kernel startup code (non-paged MM)
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* for 32-bit CPUs which has a process ID register(CP15).
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*
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*/
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#include <linux/linkage.h>
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@ -40,7 +39,11 @@
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ENTRY(stext)
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
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@ and irqs disabled
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#ifndef CONFIG_CPU_CP15
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ldr r9, =CONFIG_PROCESSOR_ID
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#else
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mrc p15, 0, r9, c0, c0 @ get processor id
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#endif
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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@ -58,6 +61,7 @@ ENTRY(stext)
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*/
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.type __after_proc_init, %function
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__after_proc_init:
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#ifdef CONFIG_CPU_CP15
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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#ifdef CONFIG_ALIGNMENT_TRAP
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orr r0, r0, #CR_A
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@ -74,6 +78,7 @@ __after_proc_init:
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bic r0, r0, #CR_I
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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#endif /* CONFIG_CPU_CP15 */
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mov pc, r13 @ clear the BSS and jump
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@ to start_kernel
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@ -221,16 +221,26 @@ void __show_regs(struct pt_regs *regs)
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processor_modes[processor_mode(regs)],
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thumb_mode(regs) ? " (T)" : "",
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get_fs() == get_ds() ? "kernel" : "user");
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#if CONFIG_CPU_CP15
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{
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unsigned int ctrl, transbase, dac;
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unsigned int ctrl;
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__asm__ (
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" mrc p15, 0, %0, c1, c0\n"
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" mrc p15, 0, %1, c2, c0\n"
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" mrc p15, 0, %2, c3, c0\n"
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: "=r" (ctrl), "=r" (transbase), "=r" (dac));
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printk("Control: %04X Table: %08X DAC: %08X\n",
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ctrl, transbase, dac);
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: "=r" (ctrl));
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printk("Control: %04X\n", ctrl);
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}
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#ifdef CONFIG_CPU_CP15_MMU
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{
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unsigned int transbase, dac;
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__asm__ (
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" mrc p15, 0, %0, c2, c0\n"
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" mrc p15, 0, %1, c3, c0\n"
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: "=r" (transbase), "=r" (dac));
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printk("Table: %08X DAC: %08X\n",
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transbase, dac);
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}
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#endif
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#endif
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}
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void show_regs(struct pt_regs * regs)
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@ -445,15 +445,15 @@ config CPU_BIG_ENDIAN
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of your chipset/board/processor.
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config CPU_ICACHE_DISABLE
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bool "Disable I-Cache"
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depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
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bool "Disable I-Cache (I-bit)"
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depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
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help
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Say Y here to disable the processor instruction cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_DISABLE
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bool "Disable D-Cache"
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depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
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bool "Disable D-Cache (C-bit)"
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depends on CPU_CP15
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help
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Say Y here to disable the processor data cache. Unless
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you have a reason not to or are unsure, say N.
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@ -29,9 +29,13 @@ ENTRY(v4_flush_user_cache_all)
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* Clean and invalidate the entire cache.
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*/
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ENTRY(v4_flush_kern_cache_all)
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#ifdef CPU_CP15
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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mov pc, lr
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#else
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/* FALLTHROUGH */
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#endif
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/*
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* flush_user_cache_range(start, end, flags)
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@ -44,9 +48,13 @@ ENTRY(v4_flush_kern_cache_all)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v4_flush_user_cache_range)
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#ifdef CPU_CP15
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mov ip, #0
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mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
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mov pc, lr
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#else
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/* FALLTHROUGH */
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#endif
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/*
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* coherent_kern_range(start, end)
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@ -108,8 +116,10 @@ ENTRY(v4_dma_inv_range)
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* - end - virtual end address
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*/
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ENTRY(v4_dma_flush_range)
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#ifdef CPU_CP15
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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#endif
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/* FALLTHROUGH */
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/*
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@ -46,6 +46,7 @@
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#define CPUID_TCM 2
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#define CPUID_TLBTYPE 3
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#ifdef CONFIG_CPU_CP15
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#define read_cpuid(reg) \
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({ \
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unsigned int __val; \
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@ -55,6 +56,9 @@
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: "cc"); \
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__val; \
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})
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#else
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#define read_cpuid(reg) (processor_id)
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#endif
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/*
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* This is used to ensure the compiler did actually allocate the register we
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