ASoC: fsl_xcvr: Add support for i.MX95 platform
On i.MX95, the XCVR uses a new PLL in the PHY, which is General Purpose (GP) PLL. Add GP PLL configuration support in the driver and add the 'pll_ver' flag to distinguish different PLL on different platforms. The XCVR also use PHY but limited for SPDIF only case Add 'use_phy' flag to distinguish these platforms. When there are 'pll8k' and 'pll11k' clock existing, the clock source of 'phy_clk' can be changed for different sample rate requirement. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Chancel Liu <chancel.liu@nxp.com> Link: https://msgid.link/r/1716972002-2315-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang
Mark Brown
parent
fc1277335f
commit
f13b349e3c
@ -103,6 +103,7 @@ config SND_SOC_FSL_XCVR
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select REGMAP_MMIO
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select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
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select SND_SOC_GENERIC_DMAENGINE_PCM
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select SND_SOC_FSL_UTILS
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help
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Say Y if you want to add Audio Transceiver (XCVR) support for NXP
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iMX CPUs. XCVR is a digital module that supports HDMI2.1 eARC,
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@ -15,14 +15,22 @@
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#include <sound/pcm_params.h>
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#include "fsl_xcvr.h"
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#include "fsl_utils.h"
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#include "imx-pcm.h"
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#define FSL_XCVR_CAPDS_SIZE 256
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enum fsl_xcvr_pll_verison {
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PLL_MX8MP,
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PLL_MX95,
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};
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struct fsl_xcvr_soc_data {
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const char *fw_name;
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bool spdif_only;
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bool use_edma;
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bool use_phy;
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enum fsl_xcvr_pll_verison pll_ver;
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};
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struct fsl_xcvr {
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@ -33,6 +41,8 @@ struct fsl_xcvr {
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struct clk *pll_ipg_clk;
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struct clk *phy_clk;
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struct clk *spba_clk;
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struct clk *pll8k_clk;
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struct clk *pll11k_clk;
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struct reset_control *reset;
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u8 streams;
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u32 mode;
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@ -262,10 +272,10 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
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static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
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{
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struct device *dev = &xcvr->pdev->dev;
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u32 i, div = 0, log2;
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u32 i, div = 0, log2, val;
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int ret;
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if (xcvr->soc_data->spdif_only)
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if (!xcvr->soc_data->use_phy)
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return 0;
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for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
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@ -288,45 +298,62 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
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return ret;
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}
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/* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
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FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
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switch (xcvr->soc_data->pll_ver) {
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case PLL_MX8MP:
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/* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
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FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
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/* PLL: CTRL0: DIV_INTEGER */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
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/* PLL: NUMERATOR: MFN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
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/* PLL: DENOMINATOR: MFD */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
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/* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
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udelay(25);
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/* PLL: CTRL0: Clear Hold Ring Off */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
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FSL_XCVR_PLL_CTRL0_HROFF, 0);
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udelay(100);
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if (tx) { /* TX is enabled for SPDIF only */
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/* PLL: POSTDIV: PDIV0 */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
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FSL_XCVR_PLL_PDIVx(log2, 0), 0);
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/* PLL: CTRL_SET: CLKMUX0_EN */
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/* PLL: CTRL0: DIV_INTEGER */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
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/* PLL: NUMERATOR: MFN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
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/* PLL: DENOMINATOR: MFD */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
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/* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
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} else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
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/* PLL: POSTDIV: PDIV1 */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
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FSL_XCVR_PLL_PDIVx(log2, 1), 0);
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/* PLL: CTRL_SET: CLKMUX1_EN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
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} else { /* SPDIF / ARC RX */
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/* PLL: POSTDIV: PDIV2 */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
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FSL_XCVR_PLL_PDIVx(log2, 2), 0);
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/* PLL: CTRL_SET: CLKMUX2_EN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
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FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
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udelay(25);
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/* PLL: CTRL0: Clear Hold Ring Off */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
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FSL_XCVR_PLL_CTRL0_HROFF, 0);
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udelay(100);
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if (tx) { /* TX is enabled for SPDIF only */
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/* PLL: POSTDIV: PDIV0 */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
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FSL_XCVR_PLL_PDIVx(log2, 0), 0);
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/* PLL: CTRL_SET: CLKMUX0_EN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
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} else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
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/* PLL: POSTDIV: PDIV1 */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
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FSL_XCVR_PLL_PDIVx(log2, 1), 0);
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/* PLL: CTRL_SET: CLKMUX1_EN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
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} else { /* SPDIF / ARC RX */
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/* PLL: POSTDIV: PDIV2 */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
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FSL_XCVR_PLL_PDIVx(log2, 2), 0);
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/* PLL: CTRL_SET: CLKMUX2_EN */
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
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FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
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}
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break;
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case PLL_MX95:
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val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div;
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0);
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val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT;
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0);
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR,
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fsl_xcvr_pll_cfg[i].mfd, 0);
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val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN;
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fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0);
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break;
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default:
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dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver);
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return -EINVAL;
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}
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if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
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@ -362,6 +389,8 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
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freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
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clk_disable_unprepare(xcvr->phy_clk);
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fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk,
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xcvr->pll8k_clk, xcvr->pll11k_clk, freq);
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ret = clk_set_rate(xcvr->phy_clk, freq);
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if (ret < 0) {
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dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
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@ -373,7 +402,7 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
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return ret;
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}
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if (xcvr->soc_data->spdif_only)
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if (!xcvr->soc_data->use_phy)
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return 0;
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/* Release AI interface from reset */
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ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
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@ -1017,7 +1046,7 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
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if (xcvr->soc_data->spdif_only)
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if (!xcvr->soc_data->use_phy)
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if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
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reg > FSL_XCVR_TX_DPTH_BCRR)
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return false;
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@ -1090,7 +1119,7 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
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if (xcvr->soc_data->spdif_only)
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if (!xcvr->soc_data->use_phy)
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if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
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return false;
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switch (reg) {
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@ -1234,6 +1263,8 @@ static irqreturn_t irq0_isr(int irq, void *devid)
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static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
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.fw_name = "imx/xcvr/xcvr-imx8mp.bin",
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.use_phy = true,
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.pll_ver = PLL_MX8MP,
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};
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static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
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@ -1241,9 +1272,17 @@ static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
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.use_edma = true,
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};
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static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = {
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.spdif_only = true,
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.use_phy = true,
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.use_edma = true,
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.pll_ver = PLL_MX95,
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};
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static const struct of_device_id fsl_xcvr_dt_ids[] = {
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{ .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
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{ .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
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{ .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
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@ -1287,6 +1326,9 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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return PTR_ERR(xcvr->pll_ipg_clk);
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}
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fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk,
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&xcvr->pll11k_clk);
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xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
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if (IS_ERR(xcvr->ram_addr))
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return PTR_ERR(xcvr->ram_addr);
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@ -291,4 +291,95 @@
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#define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */
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#define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */
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/* GP PLL Registers */
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#define FSL_XCVR_GP_PLL_CTRL 0x00
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#define FSL_XCVR_GP_PLL_CTRL_SET 0x04
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#define FSL_XCVR_GP_PLL_CTRL_CLR 0x08
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#define FSL_XCVR_GP_PLL_CTRL_TOG 0x0C
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#define FSL_XCVR_GP_PLL_ANA_PRG 0x10
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#define FSL_XCVR_GP_PLL_ANA_PRG_SET 0x14
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#define FSL_XCVR_GP_PLL_ANA_PRG_CLR 0x18
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#define FSL_XCVR_GP_PLL_ANA_PRG_TOG 0x1C
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#define FSL_XCVR_GP_PLL_TEST 0x20
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#define FSL_XCVR_GP_PLL_TEST_SET 0x24
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#define FSL_XCVR_GP_PLL_TEST_CLR 0x28
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#define FSL_XCVR_GP_PLL_TEST_TOG 0x2C
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#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM 0x30
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#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_SET 0x34
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#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_CLR 0x38
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#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_TOG 0x3C
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#define FSL_XCVR_GP_PLL_NUMERATOR 0x40
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#define FSL_XCVR_GP_PLL_NUMERATOR_SET 0x44
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#define FSL_XCVR_GP_PLL_NUMERATOR_CLR 0x48
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#define FSL_XCVR_GP_PLL_NUMERATOR_TOG 0x4C
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#define FSL_XCVR_GP_PLL_DENOMINATOR 0x50
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#define FSL_XCVR_GP_PLL_DENOMINATOR_SET 0x54
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#define FSL_XCVR_GP_PLL_DENOMINATOR_CLR 0x58
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#define FSL_XCVR_GP_PLL_DENOMINATOR_TOG 0x5C
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#define FSL_XCVR_GP_PLL_DIV 0x60
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#define FSL_XCVR_GP_PLL_DIV_SET 0x64
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#define FSL_XCVR_GP_PLL_DIV_CLR 0x68
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#define FSL_XCVR_GP_PLL_DIV_TOG 0x6C
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#define FSL_XCVR_GP_PLL_DFS_CTRL0 0x70
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#define FSL_XCVR_GP_PLL_DFS_CTRL0_SET 0x74
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#define FSL_XCVR_GP_PLL_DFS_CTRL0_CLR 0x78
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#define FSL_XCVR_GP_PLL_DFS_CTRL0_TOG 0x7C
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#define FSL_XCVR_GP_PLL_DFS_DIV0 0x80
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#define FSL_XCVR_GP_PLL_DFS_DIV0_SET 0x84
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#define FSL_XCVR_GP_PLL_DFS_DIV0_CLR 0x88
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#define FSL_XCVR_GP_PLL_DFS_DIV0_TOG 0x8C
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#define FSL_XCVR_GP_PLL_DFS_CTRL1 0x90
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#define FSL_XCVR_GP_PLL_DFS_CTRL1_SET 0x94
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#define FSL_XCVR_GP_PLL_DFS_CTRL1_CLR 0x98
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#define FSL_XCVR_GP_PLL_DFS_CTRL1_TOG 0x9C
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#define FSL_XCVR_GP_PLL_DFS_DIV1 0xA0
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#define FSL_XCVR_GP_PLL_DFS_DIV1_SET 0xA4
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#define FSL_XCVR_GP_PLL_DFS_DIV1_CLR 0xA8
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#define FSL_XCVR_GP_PLL_DFS_DIV1_TOG 0xAC
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#define FSL_XCVR_GP_PLL_DFS_CTRL2 0xB0
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#define FSL_XCVR_GP_PLL_DFS_CTRL2_SET 0xB4
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#define FSL_XCVR_GP_PLL_DFS_CTRL2_CLR 0xB8
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#define FSL_XCVR_GP_PLL_DFS_CTRL2_TOG 0xBC
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#define FSL_XCVR_GP_PLL_DFS_DIV2 0xC0
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#define FSL_XCVR_GP_PLL_DFS_DIV2_SET 0xC4
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#define FSL_XCVR_GP_PLL_DFS_DIV2_CLR 0xC8
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#define FSL_XCVR_GP_PLL_DFS_DIV2_TOG 0xCC
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#define FSL_XCVR_GP_PLL_DFS_CTRL3 0xD0
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#define FSL_XCVR_GP_PLL_DFS_CTRL3_SET 0xD4
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#define FSL_XCVR_GP_PLL_DFS_CTRL3_CLR 0xD8
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#define FSL_XCVR_GP_PLL_DFS_CTRL3_TOG 0xDC
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#define FSL_XCVR_GP_PLL_DFS_DIV3 0xE0
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#define FSL_XCVR_GP_PLL_DFS_DIV3_SET 0xE4
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#define FSL_XCVR_GP_PLL_DFS_DIV3_CLR 0xE8
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#define FSL_XCVR_GP_PLL_DFS_DIV3_TOG 0xEC
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#define FSL_XCVR_GP_PLL_STATUS 0xF0
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#define FSL_XCVR_GP_PLL_STATUS_SET 0xF4
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#define FSL_XCVR_GP_PLL_STATUS_CLR 0xF8
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#define FSL_XCVR_GP_PLL_STATUS_TOG 0xFC
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/* GP PLL Control Register */
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#define FSL_XCVR_GP_PLL_CTRL_LBYPASS BIT(31)
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#define FSL_XCVR_GP_PLL_CTRL_HCS BIT(16)
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#define FSL_XCVR_GP_PLL_CTRL_MSD BIT(12)
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#define FSL_XCVR_GP_PLL_CTRL_DITHER_EN3 BIT(11)
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#define FSL_XCVR_GP_PLL_CTRL_DITHER_EN2 BIT(10)
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#define FSL_XCVR_GP_PLL_CTRL_DITHER_EN1 BIT(9)
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#define FSL_XCVR_GP_PLL_CTRL_SPREADCTL BIT(8)
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#define FSL_XCVR_GP_PLL_CTRL_CLKMUX_BYPASS BIT(2)
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#define FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN BIT(1)
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#define FSL_XCVR_GP_PLL_CTRL_POWERUP BIT(0)
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|
||||
/* GP PLL Numerator Register */
|
||||
#define FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT 2
|
||||
#define FSL_XCVR_GP_PLL_NUMERATOR_MFN GENMASK(31, 2)
|
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|
||||
/* GP PLL Denominator Register */
|
||||
#define FSL_XCVR_GP_PLL_DENOMINATOR_MFD GENMASK(29, 0)
|
||||
|
||||
/* GP PLL Dividers Register */
|
||||
#define FSL_XCVR_GP_PLL_DIV_MFI_SHIFT 16
|
||||
#define FSL_XCVR_GP_PLL_DIV_MFI GENMASK(24, 16)
|
||||
#define FSL_XCVR_GP_PLL_DIV_RDIV GENMASK(15, 13)
|
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#define FSL_XCVR_GP_PLL_DIV_ODIV GENMASK(7, 0)
|
||||
|
||||
#endif /* __FSL_XCVR_H */
|
||||
|
||||
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Reference in New Issue
Block a user